From patchwork Tue Oct 13 21:25:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11837217 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 36D3215E6 for ; Wed, 14 Oct 2020 09:24:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0D6FD20709 for ; Wed, 14 Oct 2020 09:24:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="NK1OdlR3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728346AbgJNJYr (ORCPT ); Wed, 14 Oct 2020 05:24:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730676AbgJNJUC (ORCPT ); Wed, 14 Oct 2020 05:20:02 -0400 Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0ED26C0613DA for ; Tue, 13 Oct 2020 14:26:24 -0700 (PDT) Received: by mail-pf1-x441.google.com with SMTP id b26so625558pff.3 for ; Tue, 13 Oct 2020 14:26:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8emszWUEydnaDuASluTEaLP6IQxhJiyG+Sdg8L/FF9A=; b=NK1OdlR3WP11CVF2y113zjl7VJMJe3PpbX5vvN2tkTzBZDQ9Js9EotP6+HM9DR86Y6 KWEy+KX2WfMP7WQy83igiJ6GLL/BZspv3He3hTxhy963KZ4+EUSxMeorxgEhT5irtZYf xAgNPajbLPpjLycPnIG6tAENSjIXj0X164grw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8emszWUEydnaDuASluTEaLP6IQxhJiyG+Sdg8L/FF9A=; b=LlGn1Cz9eRaTEolDqRIx0a48daRy0MoCk0mZRtpvmRFX8nnC4IEqMfAJ37UawozqMB xdOsEFp9Jpd/A6o9/lVJfF3M3mOFVz+Wyi/z9Zyck1qdEkTrVzm4xJ5ysPYibPJ8ku6C Npml4RXUFzJSUkIjwNEvre6J43FBxjmSiuDw0SkvBAdEQxGgZk6OMwNLgeyOp1AdwLcf uXAshkwhUMQtF1eeq7QlDRZrRrf/iFwH10oPe6QIXznsNucaTgKAvIAV4cFNsdOO3a2S es8q1yPq7gTiUK/BgODVE/DMdYMRFa1LwNa8GN8TT8C4+JMIIf/jMphTh+GI9ZuGM07Y Ucjg== X-Gm-Message-State: AOAM532Em+r/4tiwjgTBUj/vLPEznTqZczv3Li8WCzV4zW/Zz9ZrdQ18 /Sb/Iu1ReFq0t2/Pd4XsFUf4GbxEGsJtoQ== X-Google-Smtp-Source: ABdhPJwt1IzKXrttcWDZhkMbn21U9Tie+bRQG4Zddvl3JpkIMxKMTivZJV2Ph0NiPyaJ7SjvwhTrFw== X-Received: by 2002:a63:511d:: with SMTP id f29mr1218104pgb.11.1602624383571; Tue, 13 Oct 2020 14:26:23 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:42b0:34ff:fe3d:58e6]) by smtp.gmail.com with ESMTPSA id b15sm167713pju.16.2020.10.13.14.26.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2020 14:26:23 -0700 (PDT) From: Douglas Anderson To: Bjorn Andersson , Wolfram Sang , Akash Asthana Cc: linux-i2c@vger.kernel.org, Roja Rani Yarubandi , Stephen Boyd , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, Douglas Anderson , Andy Gross , Girish Mahadevan , Karthikeyan Ramasubramanian , Mukesh Kumar Savaliya , Sagar Dharia , linux-kernel@vger.kernel.org Subject: [PATCH v2 1/3] soc: qcom: geni: More properly switch to DMA mode Date: Tue, 13 Oct 2020 14:25:28 -0700 Message-Id: <20201013142448.v2.1.Ifdb1b69fa3367b81118e16e9e4e63299980ca798@changeid> X-Mailer: git-send-email 2.28.0.1011.ga647a8990f-goog In-Reply-To: <20201013212531.428538-1-dianders@chromium.org> References: <20201013212531.428538-1-dianders@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On geni-i2c transfers using DMA, it was seen that if you program the command (I2C_READ) before calling geni_se_rx_dma_prep() that it could cause interrupts to fire. If we get unlucky, these interrupts can just keep firing (and not be handled) blocking further progress and hanging the system. In commit 02b9aec59243 ("i2c: i2c-qcom-geni: Fix DMA transfer race") we avoided that by making sure we didn't program the command until after geni_se_rx_dma_prep() was called. While that avoided the problems, it also turns out to be invalid. At least in the TX case we started seeing sporadic corrupted transfers. This is easily seen by adding an msleep() between the DMA prep and the writing of the command, which makes the problem worse. That means we need to revert that commit and find another way to fix the bogus IRQs. Specifically, after reverting commit 02b9aec59243 ("i2c: i2c-qcom-geni: Fix DMA transfer race"), I put some traces in. I found that the when the interrupts were firing like crazy: - "m_stat" had bits for M_RX_IRQ_EN, M_RX_FIFO_WATERMARK_EN set. - "dma" was set. Further debugging showed that I could make the problem happen more reliably by adding an "msleep(1)" any time after geni_se_setup_m_cmd() ran up until geni_se_rx_dma_prep() programmed the length. A rather simple fix is to change geni_se_select_dma_mode() so it's a true inverse of geni_se_select_fifo_mode() and disables all the FIFO related interrupts. Now the problematic interrupts can't fire and we can program things in the correct order without worrying. As part of this, let's also change the writel_relaxed() in the prepare function to a writel() so that our DMA is guaranteed to be prepared now that we can't rely on geni_se_setup_m_cmd()'s writel(). NOTE: the only current user of GENI_SE_DMA in mainline is i2c. Fixes: 37692de5d523 ("i2c: i2c-qcom-geni: Add bus driver for the Qualcomm GENI I2C controller") Fixes: 02b9aec59243 ("i2c: i2c-qcom-geni: Fix DMA transfer race") Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Akash Asthana Tested-by: Dmitry Baryshkov --- (no changes since v1) drivers/soc/qcom/qcom-geni-se.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index d0e4f520cff8..751a49f6534f 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -289,10 +289,23 @@ static void geni_se_select_fifo_mode(struct geni_se *se) static void geni_se_select_dma_mode(struct geni_se *se) { + u32 proto = geni_se_read_proto(se); u32 val; geni_se_irq_clear(se); + val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); + if (proto != GENI_SE_UART) { + val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); + val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); + } + writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); + + val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); + if (proto != GENI_SE_UART) + val &= ~S_CMD_DONE_EN; + writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); + val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); val |= GENI_DMA_MODE_EN; writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); @@ -651,7 +664,7 @@ int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L); writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H); writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR); - writel_relaxed(len, se->base + SE_DMA_TX_LEN); + writel(len, se->base + SE_DMA_TX_LEN); return 0; } EXPORT_SYMBOL(geni_se_tx_dma_prep); @@ -688,7 +701,7 @@ int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H); /* RX does not have EOT buffer type bit. So just reset RX_ATTR */ writel_relaxed(0, se->base + SE_DMA_RX_ATTR); - writel_relaxed(len, se->base + SE_DMA_RX_LEN); + writel(len, se->base + SE_DMA_RX_LEN); return 0; } EXPORT_SYMBOL(geni_se_rx_dma_prep);