| Message ID | 20201102171416.654337-4-jcrouse@codeaurora.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | iommu/arm-smmu: Add adreno-smmu implementation and bindings | expand |
On 2020-11-02 17:14, Jordan Crouse wrote: > Every Qcom Adreno GPU has an embedded SMMU for its own use. These > devices depend on unique features such as split pagetables, > different stall/halt requirements and other settings. Identify them > with a compatible string so that they can be identified in the > arm-smmu implementation specific code. > > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Rob Clark <robdclark@chromium.org> > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > > Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > index 503160a7b9a0..3b63f2ae24db 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > @@ -28,8 +28,6 @@ properties: > - enum: > - qcom,msm8996-smmu-v2 > - qcom,msm8998-smmu-v2 > - - qcom,sc7180-smmu-v2 > - - qcom,sdm845-smmu-v2 What about the "Apps SMMU" instances? Those are distinct and don't have/need the GPU special behaviour, right? Robin. > - const: qcom,smmu-v2 > > - description: Qcom SoCs implementing "arm,mmu-500" > @@ -40,6 +38,13 @@ properties: > - qcom,sm8150-smmu-500 > - qcom,sm8250-smmu-500 > - const: arm,mmu-500 > + - description: Qcom Adreno GPUs implementing "arm,smmu-v2" > + items: > + - enum: > + - qcom,sc7180-smmu-v2 > + - qcom,sdm845-smmu-v2 > + - const: qcom,adreno-smmu > + - const: qcom,smmu-v2 > - description: Marvell SoCs implementing "arm,mmu-500" > items: > - const: marvell,ap806-smmu-500 >
On 2020-11-02 18:22, Robin Murphy wrote: > On 2020-11-02 17:14, Jordan Crouse wrote: >> Every Qcom Adreno GPU has an embedded SMMU for its own use. These >> devices depend on unique features such as split pagetables, >> different stall/halt requirements and other settings. Identify them >> with a compatible string so that they can be identified in the >> arm-smmu implementation specific code. >> >> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> >> Reviewed-by: Rob Herring <robh@kernel.org> >> Signed-off-by: Rob Clark <robdclark@chromium.org> >> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> >> --- >> >> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 9 +++++++-- >> 1 file changed, 7 insertions(+), 2 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >> b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >> index 503160a7b9a0..3b63f2ae24db 100644 >> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >> @@ -28,8 +28,6 @@ properties: >> - enum: >> - qcom,msm8996-smmu-v2 >> - qcom,msm8998-smmu-v2 >> - - qcom,sc7180-smmu-v2 >> - - qcom,sdm845-smmu-v2 > > What about the "Apps SMMU" instances? Those are distinct and don't > have/need the GPU special behaviour, right? Oh, having looked at patch #4, which prompted me go and look at the 845 DTSI in context, now I realise the subtlety I overlooked. So I guess it really was worth resending, ha! Sorry for being thick :) Reviewed-by: Robin Murphy <robin.murphy@arm.com> > > Robin. > >> - const: qcom,smmu-v2 >> - description: Qcom SoCs implementing "arm,mmu-500" >> @@ -40,6 +38,13 @@ properties: >> - qcom,sm8150-smmu-500 >> - qcom,sm8250-smmu-500 >> - const: arm,mmu-500 >> + - description: Qcom Adreno GPUs implementing "arm,smmu-v2" >> + items: >> + - enum: >> + - qcom,sc7180-smmu-v2 >> + - qcom,sdm845-smmu-v2 >> + - const: qcom,adreno-smmu >> + - const: qcom,smmu-v2 >> - description: Marvell SoCs implementing "arm,mmu-500" >> items: >> - const: marvell,ap806-smmu-500 >>
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 503160a7b9a0..3b63f2ae24db 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -28,8 +28,6 @@ properties: - enum: - qcom,msm8996-smmu-v2 - qcom,msm8998-smmu-v2 - - qcom,sc7180-smmu-v2 - - qcom,sdm845-smmu-v2 - const: qcom,smmu-v2 - description: Qcom SoCs implementing "arm,mmu-500" @@ -40,6 +38,13 @@ properties: - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - const: arm,mmu-500 + - description: Qcom Adreno GPUs implementing "arm,smmu-v2" + items: + - enum: + - qcom,sc7180-smmu-v2 + - qcom,sdm845-smmu-v2 + - const: qcom,adreno-smmu + - const: qcom,smmu-v2 - description: Marvell SoCs implementing "arm,mmu-500" items: - const: marvell,ap806-smmu-500