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[1/3] dt-bindings: interconnect: sdm845: Add IDs for the QUP ports

Message ID 20201105135211.7160-1-georgi.djakov@linaro.org (mailing list archive)
State Accepted
Commit 8742bb4bf203814b09572b615b5aeab000bf6248
Headers show
Series [1/3] dt-bindings: interconnect: sdm845: Add IDs for the QUP ports | expand

Commit Message

Georgi Djakov Nov. 5, 2020, 1:52 p.m. UTC
The QUP ports exist in the topology, but are not exposed as an
endpoints in DT. Fix this by creating IDs and attach them to their
NoCs, so that the various QUP drivers (i2c/spi/uart etc.) are able
to request their interconnect paths and scale their bandwidth.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
 include/dt-bindings/interconnect/qcom,sdm845.h | 2 ++
 1 file changed, 2 insertions(+)

Comments

Rob Herring (Arm) Nov. 9, 2020, 8:02 p.m. UTC | #1
On Thu, 05 Nov 2020 15:52:09 +0200, Georgi Djakov wrote:
> The QUP ports exist in the topology, but are not exposed as an
> endpoints in DT. Fix this by creating IDs and attach them to their
> NoCs, so that the various QUP drivers (i2c/spi/uart etc.) are able
> to request their interconnect paths and scale their bandwidth.
> 
> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
> ---
>  include/dt-bindings/interconnect/qcom,sdm845.h | 2 ++
>  1 file changed, 2 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>
Bjorn Andersson Nov. 11, 2020, 4:37 a.m. UTC | #2
On Thu 05 Nov 07:52 CST 2020, Georgi Djakov wrote:

> The QUP ports exist in the topology, but are not exposed as an
> endpoints in DT. Fix this by creating IDs and attach them to their
> NoCs, so that the various QUP drivers (i2c/spi/uart etc.) are able
> to request their interconnect paths and scale their bandwidth.
> 
> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Regards,
Bjorn

> ---
>  include/dt-bindings/interconnect/qcom,sdm845.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/include/dt-bindings/interconnect/qcom,sdm845.h b/include/dt-bindings/interconnect/qcom,sdm845.h
> index 290be38f40e6..67b500e24915 100644
> --- a/include/dt-bindings/interconnect/qcom,sdm845.h
> +++ b/include/dt-bindings/interconnect/qcom,sdm845.h
> @@ -19,6 +19,7 @@
>  #define SLAVE_A1NOC_SNOC		7
>  #define SLAVE_SERVICE_A1NOC		8
>  #define SLAVE_ANOC_PCIE_A1NOC_SNOC	9
> +#define MASTER_QUP_1			10
>  
>  #define MASTER_A2NOC_CFG		0
>  #define MASTER_QDSS_BAM			1
> @@ -32,6 +33,7 @@
>  #define SLAVE_A2NOC_SNOC		9
>  #define SLAVE_ANOC_PCIE_SNOC		10
>  #define SLAVE_SERVICE_A2NOC		11
> +#define MASTER_QUP_2			12
>  
>  #define MASTER_SPDM			0
>  #define MASTER_TIC			1
patchwork-bot+linux-arm-msm@kernel.org Nov. 30, 2020, 7 p.m. UTC | #3
Hello:

This series was applied to qcom/linux.git (refs/heads/for-next):

On Thu,  5 Nov 2020 15:52:09 +0200 you wrote:
> The QUP ports exist in the topology, but are not exposed as an
> endpoints in DT. Fix this by creating IDs and attach them to their
> NoCs, so that the various QUP drivers (i2c/spi/uart etc.) are able
> to request their interconnect paths and scale their bandwidth.
> 
> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
> 
> [...]

Here is the summary with links:
  - [1/3] dt-bindings: interconnect: sdm845: Add IDs for the QUP ports
    https://git.kernel.org/qcom/c/8742bb4bf203
  - [2/3] interconnect: qcom: sdm845: Add the missing nodes for QUP
    https://git.kernel.org/qcom/c/cd5fc457e5d2
  - [3/3] arm64: dts: sdm845: Add interconnect properties for QUP
    https://git.kernel.org/qcom/c/05b801afb7d7

You are awesome, thank you!
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diff mbox series

Patch

diff --git a/include/dt-bindings/interconnect/qcom,sdm845.h b/include/dt-bindings/interconnect/qcom,sdm845.h
index 290be38f40e6..67b500e24915 100644
--- a/include/dt-bindings/interconnect/qcom,sdm845.h
+++ b/include/dt-bindings/interconnect/qcom,sdm845.h
@@ -19,6 +19,7 @@ 
 #define SLAVE_A1NOC_SNOC		7
 #define SLAVE_SERVICE_A1NOC		8
 #define SLAVE_ANOC_PCIE_A1NOC_SNOC	9
+#define MASTER_QUP_1			10
 
 #define MASTER_A2NOC_CFG		0
 #define MASTER_QDSS_BAM			1
@@ -32,6 +33,7 @@ 
 #define SLAVE_A2NOC_SNOC		9
 #define SLAVE_ANOC_PCIE_SNOC		10
 #define SLAVE_SERVICE_A2NOC		11
+#define MASTER_QUP_2			12
 
 #define MASTER_SPDM			0
 #define MASTER_TIC			1