diff mbox series

[v3,1/4] ARM: dts: qcom: msm8974: add gpu support

Message ID 20210125180427.3109269-1-iskren.chernev@gmail.com (mailing list archive)
State Superseded
Headers show
Series [v3,1/4] ARM: dts: qcom: msm8974: add gpu support | expand

Commit Message

Iskren Chernev Jan. 25, 2021, 6:04 p.m. UTC 
From: Brian Masney <masneyb@onstation.org>

Add support for the a3xx GPU. opp_table is chosen to include lower
frequencies common to all different msm8974 variants.

Signed-off-by: Brian Masney <masneyb@onstation.org>
[iskren.chernev@gmail.com: change opp-table values in v3]
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
---
Changes in v3:
- change opp-table as suggested by Konrad Dybcio
- remove tested-by/reviewed-by because of code changes

v2: https://lkml.org/lkml/2021/1/24/142
v1: https://lkml.org/lkml/2020/12/30/322

 arch/arm/boot/dts/qcom-msm8974.dtsi | 45 +++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)


base-commit: 226871e2eda4832d94c3239add7e52ad17b81ce5
--
2.30.0
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 51f5f904f9eb9..683622d6c8954 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1399,6 +1399,51 @@  cnoc: interconnect@fc480000 {
 			         <&rpmcc RPM_SMD_CNOC_A_CLK>;
 		};

+		gpu_opp_table: opp_table {
+			status = "disabled";
+
+			compatible = "operating-points-v2";
+
+			opp-320000000 {
+				opp-hz = /bits/ 64 <320000000>;
+			};
+
+			opp-200000000 {
+				opp-hz = /bits/ 64 <200000000>;
+			};
+
+			opp-27000000 {
+				opp-hz = /bits/ 64 <27000000>;
+			};
+		};
+
+		gpu: adreno@fdb00000 {
+			status = "disabled";
+
+			compatible = "qcom,adreno-330.2",
+			             "qcom,adreno";
+			reg = <0xfdb00000 0x10000>;
+			reg-names = "kgsl_3d0_reg_memory";
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "kgsl_3d0_irq";
+			clock-names = "core",
+			              "iface",
+			              "mem_iface";
+			clocks = <&mmcc OXILI_GFX3D_CLK>,
+			         <&mmcc OXILICX_AHB_CLK>,
+			         <&mmcc OXILICX_AXI_CLK>;
+			sram = <&gmu_sram>;
+			power-domains = <&mmcc OXILICX_GDSC>;
+			operating-points-v2 = <&gpu_opp_table>;
+
+			interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>,
+			                <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>;
+			interconnect-names = "gfx-mem",
+			                     "ocmem";
+
+			// iommus = <&gpu_iommu 0>;
+		};
+
 		mdss: mdss@fd900000 {
 			status = "disabled";