| Message ID | 20210320025942.487916-1-leo.yan@linaro.org (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | arm64: dts: msm8916: Enable CoreSight STM component | expand |
Hi Mike, On Sat, Mar 20, 2021 at 10:59:42AM +0800, Leo Yan wrote: > From: Georgi Djakov <georgi.djakov@linaro.org> > > Add DT binding for CoreSight System Trace Macrocell (STM) on msm8916, > which can benefit the CoreSight development on DB410c. For the DT binding for CoreSight STM on DB410c, I have one question: Do you know there have any CTI is conntected to STM so that the DT binding needs to reflect the connection? If this is the case, we should update the DT binding for CTI node as well. Thanks, Leo > > Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> > Signed-off-by: Leo Yan <leo.yan@linaro.org> > --- > arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 1 + > arch/arm64/boot/dts/qcom/msm8916.dtsi | 27 +++++++++++++++++++++++ > 2 files changed, 28 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi > index 3a9538e1ec97..dd87e5d739ab 100644 > --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi > +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi > @@ -406,6 +406,7 @@ &wcd_codec { > &etm1 { status = "okay"; }; > &etm2 { status = "okay"; }; > &etm3 { status = "okay"; }; > +&stm { status = "okay"; }; > &etr { status = "okay"; }; > &funnel0 { status = "okay"; }; > &funnel1 { status = "okay"; }; > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index 402e891a84ab..892f1772e53c 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi > @@ -562,6 +562,13 @@ funnel0_in4: endpoint { > remote-endpoint = <&funnel1_out>; > }; > }; > + > + port@7 { > + reg = <7>; > + funnel0_in7: endpoint { > + remote-endpoint = <&stm_out>; > + }; > + }; > }; > > out-ports { > @@ -882,6 +889,26 @@ etm3_out: endpoint { > }; > }; > > + stm: stm@802000 { > + compatible = "arm,coresight-stm", "arm,primecell"; > + reg = <0x802000 0x1000>, > + <0x9280000 0x180000>; > + reg-names = "stm-base", "stm-stimulus-base"; > + > + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; > + clock-names = "apb_pclk", "atclk"; > + > + status = "disabled"; > + > + out-ports { > + port { > + stm_out: endpoint { > + remote-endpoint = <&funnel0_in7>; > + }; > + }; > + }; > + }; > + > msmgpio: pinctrl@1000000 { > compatible = "qcom,msm8916-pinctrl"; > reg = <0x01000000 0x300000>; > -- > 2.25.1 >
Hi Leo, On Sat, Mar 20, 2021 at 10:59:42AM +0800, Leo Yan wrote: > From: Georgi Djakov <georgi.djakov@linaro.org> > > Add DT binding for CoreSight System Trace Macrocell (STM) on msm8916, > which can benefit the CoreSight development on DB410c. > > Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> > Signed-off-by: Leo Yan <leo.yan@linaro.org> > --- > arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 1 + > arch/arm64/boot/dts/qcom/msm8916.dtsi | 27 +++++++++++++++++++++++ > 2 files changed, 28 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi > index 3a9538e1ec97..dd87e5d739ab 100644 > --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi > +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi > @@ -406,6 +406,7 @@ &wcd_codec { > &etm1 { status = "okay"; }; > &etm2 { status = "okay"; }; > &etm3 { status = "okay"; }; > +&stm { status = "okay"; }; > &etr { status = "okay"; }; > &funnel0 { status = "okay"; }; > &funnel1 { status = "okay"; }; This is alphabetically ordered so &stm should be on the line before &tpiu. > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index 402e891a84ab..892f1772e53c 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi > [...] > @@ -882,6 +889,26 @@ etm3_out: endpoint { > }; > }; > > + stm: stm@802000 { And these nodes are sorted by their unit address (0x802000), so stm@802000 should be the first coresight node, before cti@810000. > + compatible = "arm,coresight-stm", "arm,primecell"; > + reg = <0x802000 0x1000>, > + <0x9280000 0x180000>; And please pad these addresses with zeroes so the order is more easily visible, i.e. + reg = <0x00802000 0x1000>, + <0x09280000 0x180000>; Thanks! Stephan
On Sat, Mar 20, 2021 at 04:35:20PM +0100, Stephan Gerhold wrote: > Hi Leo, > > On Sat, Mar 20, 2021 at 10:59:42AM +0800, Leo Yan wrote: > > From: Georgi Djakov <georgi.djakov@linaro.org> > > > > Add DT binding for CoreSight System Trace Macrocell (STM) on msm8916, > > which can benefit the CoreSight development on DB410c. > > > > Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> > > Signed-off-by: Leo Yan <leo.yan@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 1 + > > arch/arm64/boot/dts/qcom/msm8916.dtsi | 27 +++++++++++++++++++++++ > > 2 files changed, 28 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi > > index 3a9538e1ec97..dd87e5d739ab 100644 > > --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi > > +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi > > @@ -406,6 +406,7 @@ &wcd_codec { > > &etm1 { status = "okay"; }; > > &etm2 { status = "okay"; }; > > &etm3 { status = "okay"; }; > > +&stm { status = "okay"; }; > > &etr { status = "okay"; }; > > &funnel0 { status = "okay"; }; > > &funnel1 { status = "okay"; }; > > This is alphabetically ordered so &stm should be on the line before &tpiu. > > > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi > > index 402e891a84ab..892f1772e53c 100644 > > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi > > [...] > > @@ -882,6 +889,26 @@ etm3_out: endpoint { > > }; > > }; > > > > + stm: stm@802000 { > > And these nodes are sorted by their unit address (0x802000), > so stm@802000 should be the first coresight node, before cti@810000. > > > + compatible = "arm,coresight-stm", "arm,primecell"; > > + reg = <0x802000 0x1000>, > > + <0x9280000 0x180000>; > > And please pad these addresses with zeroes so the order is more easily > visible, i.e. > > + reg = <0x00802000 0x1000>, > + <0x09280000 0x180000>; Good suggestions, Stephan! Have sent patch v2 for this. Thank you, Leo
Hi Leo, There are additional CTI components on the DB410c - I think there is information on base addresses for these - but there is no information on connectivity between the CTIs and any components such as STM / ETR etc for any of the in / out signal lines. Therefore we omitted these from the original DT when adding the other CTI devices. It could well be that there are signals from the STM to a CTI, and if the information could be found then it would be useful to add - but I have not seen this information anywhere - and it is the sort of thing that is often missed out of hardware manuals. It might be possible to deduce some information using the Coresight intergration management registers - but this would involve a lot of trial and error testing Regards Mike On Sat, 20 Mar 2021 at 03:05, Leo Yan <leo.yan@linaro.org> wrote: > > Hi Mike, > > On Sat, Mar 20, 2021 at 10:59:42AM +0800, Leo Yan wrote: > > From: Georgi Djakov <georgi.djakov@linaro.org> > > > > Add DT binding for CoreSight System Trace Macrocell (STM) on msm8916, > > which can benefit the CoreSight development on DB410c. > > For the DT binding for CoreSight STM on DB410c, I have one question: > > Do you know there have any CTI is conntected to STM so that the DT > binding needs to reflect the connection? If this is the case, we > should update the DT binding for CTI node as well. > > Thanks, > Leo > > > > > Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> > > Signed-off-by: Leo Yan <leo.yan@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 1 + > > arch/arm64/boot/dts/qcom/msm8916.dtsi | 27 +++++++++++++++++++++++ > > 2 files changed, 28 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi > > index 3a9538e1ec97..dd87e5d739ab 100644 > > --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi > > +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi > > @@ -406,6 +406,7 @@ &wcd_codec { > > &etm1 { status = "okay"; }; > > &etm2 { status = "okay"; }; > > &etm3 { status = "okay"; }; > > +&stm { status = "okay"; }; > > &etr { status = "okay"; }; > > &funnel0 { status = "okay"; }; > > &funnel1 { status = "okay"; }; > > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi > > index 402e891a84ab..892f1772e53c 100644 > > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi > > @@ -562,6 +562,13 @@ funnel0_in4: endpoint { > > remote-endpoint = <&funnel1_out>; > > }; > > }; > > + > > + port@7 { > > + reg = <7>; > > + funnel0_in7: endpoint { > > + remote-endpoint = <&stm_out>; > > + }; > > + }; > > }; > > > > out-ports { > > @@ -882,6 +889,26 @@ etm3_out: endpoint { > > }; > > }; > > > > + stm: stm@802000 { > > + compatible = "arm,coresight-stm", "arm,primecell"; > > + reg = <0x802000 0x1000>, > > + <0x9280000 0x180000>; > > + reg-names = "stm-base", "stm-stimulus-base"; > > + > > + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; > > + clock-names = "apb_pclk", "atclk"; > > + > > + status = "disabled"; > > + > > + out-ports { > > + port { > > + stm_out: endpoint { > > + remote-endpoint = <&funnel0_in7>; > > + }; > > + }; > > + }; > > + }; > > + > > msmgpio: pinctrl@1000000 { > > compatible = "qcom,msm8916-pinctrl"; > > reg = <0x01000000 0x300000>; > > -- > > 2.25.1 > >
Hi Mike, On Wed, Mar 24, 2021 at 09:22:31PM +0000, Mike Leach wrote: > Hi Leo, > > There are additional CTI components on the DB410c - I think there is > information on base addresses for these - but there is no information > on connectivity between the CTIs and any components such as STM / ETR > etc for any of the in / out signal lines. > Therefore we omitted these from the original DT when adding the other > CTI devices. > > It could well be that there are signals from the STM to a CTI, and if > the information could be found then it would be useful to add - but I > have not seen this information anywhere - and it is the sort of thing > that is often missed out of hardware manuals. > It might be possible to deduce some information using the Coresight > intergration management registers - but this would involve a lot of > trial and error testing Okay, let's firstly merge the STM binding patch and later can consider to enable DT binding between CTI and STM if have sufficient info. Thanks a lot for confirmation. Leo
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 3a9538e1ec97..dd87e5d739ab 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -406,6 +406,7 @@ &wcd_codec { &etm1 { status = "okay"; }; &etm2 { status = "okay"; }; &etm3 { status = "okay"; }; +&stm { status = "okay"; }; &etr { status = "okay"; }; &funnel0 { status = "okay"; }; &funnel1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 402e891a84ab..892f1772e53c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -562,6 +562,13 @@ funnel0_in4: endpoint { remote-endpoint = <&funnel1_out>; }; }; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; }; out-ports { @@ -882,6 +889,26 @@ etm3_out: endpoint { }; }; + stm: stm@802000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x802000 0x1000>, + <0x9280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + status = "disabled"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel0_in7>; + }; + }; + }; + }; + msmgpio: pinctrl@1000000 { compatible = "qcom,msm8916-pinctrl"; reg = <0x01000000 0x300000>;