[5/5] clk: qcom: a53-pll: Add MSM8939 a53pll clocks

Commit Message

Shawn Guo May 4, 2021, 5:28 a.m. UTC

It adds support for MSM8939 a53pll clock of Cluster0, Cluster1 and CCI
(Cache Coherent Interconnect).  The frequency data comes from vendor
kernel.

Signed-off-by: Shawn Guo <[e-mail]>
---
 drivers/clk/qcom/a53-pll.c | 42 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

Comments

Stephen Boyd June 28, 2021, 12:24 a.m. UTC | #1

Quoting Shawn Guo (2021-05-03 22:28:44)
> diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c
> index bfa048dc01ec..8c6f8bcc6128 100644
> --- a/drivers/clk/qcom/a53-pll.c
> +++ b/drivers/clk/qcom/a53-pll.c
[..]
> +       { 1651200000, 86, 0x0, 0x1, 0 },
> +       { 1689600000, 88, 0x0, 0x1, 0 },
> +       { 1708800000, 89, 0x0, 0x1, 0 },
> +};
> +
> +static const struct pll_freq_tbl msm8939_cci_freq[] = {
> +       { 403200000, 21, 0x0, 0x1, 0 },
> +       { 595200000, 31, 0x0, 0x1, 0 },
> +};
> +
>  static const struct regmap_config a53pll_regmap_config = {
>         .reg_bits               = 32,
>         .reg_stride             = 4,
> @@ -98,6 +137,9 @@ static int qcom_a53pll_probe(struct platform_device *pdev)
>  
>  static const struct of_device_id qcom_a53pll_match_table[] = {
>         { .compatible = "qcom,msm8916-a53pll", .data = msm8916_freq },
> +       { .compatible = "qcom,msm8939-a53pll-c0", .data = &msm8939_c0_freq },
> +       { .compatible = "qcom,msm8939-a53pll-c1", .data = &msm8939_c1_freq },
> +       { .compatible = "qcom,msm8939-a53pll-cci", .data = &msm8939_cci_freq },

Can we push these compatibles and tables into an OPP table? Then the
frequency plan would be an opp-table binding and the driver can drive
the multiplier on XO (probably l_val) without having to hardcode it here
in the driver. It does mean we spend a bit more time at probe detecting
the frequency plan, but it would at least avoid the concern that Rob has
with multiple compatibles and probably make it easier to handle CPU
frequencies anyway.

Patch

diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c
index bfa048dc01ec..8c6f8bcc6128 100644
--- a/drivers/clk/qcom/a53-pll.c
+++ b/drivers/clk/qcom/a53-pll.c
@@ -26,6 +26,45 @@  static const struct pll_freq_tbl msm8916_freq[] = {
 	{ }
 };
 
+static const struct pll_freq_tbl msm8939_c0_freq[] = {
+	{  998400000,  52, 0x0, 0x1, 0 },
+	{ 1113600000,  58, 0x0, 0x1, 0 },
+	{ 1209600000,  63, 0x0, 0x1, 0 },
+};
+
+static const struct pll_freq_tbl msm8939_c1_freq[] = {
+	{  652800000, 34, 0x0, 0x1, 0 },
+	{  691200000, 36, 0x0, 0x1, 0 },
+	{  729600000, 38, 0x0, 0x1, 0 },
+	{  806400000, 42, 0x0, 0x1, 0 },
+	{  844800000, 44, 0x0, 0x1, 0 },
+	{  883200000, 46, 0x0, 0x1, 0 },
+	{  960000000, 50, 0x0, 0x1, 0 },
+	{  998400000, 52, 0x0, 0x1, 0 },
+	{ 1036800000, 54, 0x0, 0x1, 0 },
+	{ 1113600000, 58, 0x0, 0x1, 0 },
+	{ 1209600000, 63, 0x0, 0x1, 0 },
+	{ 1190400000, 62, 0x0, 0x1, 0 },
+	{ 1267200000, 66, 0x0, 0x1, 0 },
+	{ 1344000000, 70, 0x0, 0x1, 0 },
+	{ 1363200000, 71, 0x0, 0x1, 0 },
+	{ 1420800000, 74, 0x0, 0x1, 0 },
+	{ 1459200000, 76, 0x0, 0x1, 0 },
+	{ 1497600000, 78, 0x0, 0x1, 0 },
+	{ 1536000000, 80, 0x0, 0x1, 0 },
+	{ 1574400000, 82, 0x0, 0x1, 0 },
+	{ 1612800000, 84, 0x0, 0x1, 0 },
+	{ 1632000000, 85, 0x0, 0x1, 0 },
+	{ 1651200000, 86, 0x0, 0x1, 0 },
+	{ 1689600000, 88, 0x0, 0x1, 0 },
+	{ 1708800000, 89, 0x0, 0x1, 0 },
+};
+
+static const struct pll_freq_tbl msm8939_cci_freq[] = {
+	{ 403200000, 21, 0x0, 0x1, 0 },
+	{ 595200000, 31, 0x0, 0x1, 0 },
+};
+
 static const struct regmap_config a53pll_regmap_config = {
 	.reg_bits		= 32,
 	.reg_stride		= 4,
@@ -98,6 +137,9 @@  static int qcom_a53pll_probe(struct platform_device *pdev)
 
 static const struct of_device_id qcom_a53pll_match_table[] = {
 	{ .compatible = "qcom,msm8916-a53pll", .data = msm8916_freq },
+	{ .compatible = "qcom,msm8939-a53pll-c0", .data = &msm8939_c0_freq },
+	{ .compatible = "qcom,msm8939-a53pll-c1", .data = &msm8939_c1_freq },
+	{ .compatible = "qcom,msm8939-a53pll-cci", .data = &msm8939_cci_freq },
 	{ }
 };