Message ID | 20210608222926.2707768-2-thara.gopinath@linaro.org (mailing list archive) |
---|---|
State | Superseded |
Headers | show |
Series | Introduce LMh driver for Qualcomm SoCs | expand |
Hi Thara, I love your patch! Perhaps something to improve: [auto build test WARNING on robh/for-next] [also build test WARNING on pm/linux-next linus/master v5.13-rc5 next-20210608] [cannot apply to thermal/next] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Thara-Gopinath/Introduce-LMh-driver-for-Qualcomm-SoCs/20210609-063135 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next config: powerpc-randconfig-r024-20210608 (attached as .config) compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project d2012d965d60c3258b3a69d024491698f8aec386) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install powerpc cross compiling tool for clang build # apt-get install binutils-powerpc-linux-gnu # https://github.com/0day-ci/linux/commit/bd39209abfb69da45acdc24c969d69620106f24e git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Thara-Gopinath/Introduce-LMh-driver-for-Qualcomm-SoCs/20210609-063135 git checkout bd39209abfb69da45acdc24c969d69620106f24e # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=powerpc If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com> All warnings (new ones prefixed by >>): In file included from drivers/mmc/host/sdhci-msm.c:8: In file included from include/linux/module.h:12: In file included from include/linux/list.h:9: In file included from include/linux/kernel.h:12: In file included from include/linux/bitops.h:32: In file included from arch/powerpc/include/asm/bitops.h:62: arch/powerpc/include/asm/barrier.h:49:9: warning: '__lwsync' macro redefined [-Wmacro-redefined] #define __lwsync() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory") ^ <built-in>:308:9: note: previous definition is here #define __lwsync __builtin_ppc_lwsync ^ In file included from drivers/mmc/host/sdhci-msm.c:16: >> include/linux/qcom_scm.h:180:5: warning: no previous prototype for function 'qcom_scm_lmh_dcvsh' [-Wmissing-prototypes] int qcom_scm_lmh_dcvsh(u32 *payload, u32 payload_size, u64 limit_node, ^ include/linux/qcom_scm.h:180:1: note: declare 'static' if the function is not intended to be used outside of this translation unit int qcom_scm_lmh_dcvsh(u32 *payload, u32 payload_size, u64 limit_node, ^ static >> include/linux/qcom_scm.h:183:5: warning: no previous prototype for function 'qcom_scm_lmh_profile_change' [-Wmissing-prototypes] int qcom_scm_lmh_profile_change(u32 profile_id) { return -ENODEV; } ^ include/linux/qcom_scm.h:183:1: note: declare 'static' if the function is not intended to be used outside of this translation unit int qcom_scm_lmh_profile_change(u32 profile_id) { return -ENODEV; } ^ static >> include/linux/qcom_scm.h:185:6: warning: no previous prototype for function 'qcom_scm_lmh_dcvsh_available' [-Wmissing-prototypes] bool qcom_scm_lmh_dcvsh_available(void) { return -ENODEV; } ^ include/linux/qcom_scm.h:185:1: note: declare 'static' if the function is not intended to be used outside of this translation unit bool qcom_scm_lmh_dcvsh_available(void) { return -ENODEV; } ^ static 4 warnings generated. Kconfig warnings: (for reference only) WARNING: unmet direct dependencies detected for HOTPLUG_CPU Depends on SMP && (PPC_PSERIES || PPC_PMAC || PPC_POWERNV || FSL_SOC_BOOKE Selected by - PM_SLEEP_SMP && SMP && (ARCH_SUSPEND_POSSIBLE || ARCH_HIBERNATION_POSSIBLE && PM_SLEEP vim +/qcom_scm_lmh_dcvsh +180 include/linux/qcom_scm.h 140 141 static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) 142 { return -ENODEV; } 143 static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) 144 { return -ENODEV; } 145 146 static inline bool qcom_scm_restore_sec_cfg_available(void) { return false; } 147 static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) 148 { return -ENODEV; } 149 static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) 150 { return -ENODEV; } 151 static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) 152 { return -ENODEV; } 153 extern inline int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size, 154 u32 cp_nonpixel_start, 155 u32 cp_nonpixel_size) 156 { return -ENODEV; } 157 static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, 158 unsigned int *src, const struct qcom_scm_vmperm *newvm, 159 unsigned int dest_cnt) { return -ENODEV; } 160 161 static inline bool qcom_scm_ocmem_lock_available(void) { return false; } 162 static inline int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, 163 u32 size, u32 mode) { return -ENODEV; } 164 static inline int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, 165 u32 offset, u32 size) { return -ENODEV; } 166 167 static inline bool qcom_scm_ice_available(void) { return false; } 168 static inline int qcom_scm_ice_invalidate_key(u32 index) { return -ENODEV; } 169 static inline int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size, 170 enum qcom_scm_ice_cipher cipher, 171 u32 data_unit_size) { return -ENODEV; } 172 173 static inline bool qcom_scm_hdcp_available(void) { return false; } 174 static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, 175 u32 *resp) { return -ENODEV; } 176 177 static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en) 178 { return -ENODEV; } 179 > 180 int qcom_scm_lmh_dcvsh(u32 *payload, u32 payload_size, u64 limit_node, 181 u32 node_id, u64 version) 182 { return -ENODEV; } > 183 int qcom_scm_lmh_profile_change(u32 profile_id) { return -ENODEV; } 184 > 185 bool qcom_scm_lmh_dcvsh_available(void) { return -ENODEV; } --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index ee9cb545e73b..0259e9ffb8a1 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -1147,6 +1147,53 @@ int qcom_scm_qsmmu500_wait_safe_toggle(bool en) } EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle); +bool qcom_scm_lmh_dcvsh_available(void) +{ + return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_LMH, QCOM_SCM_LMH_LIMIT_DCVSH); +} +EXPORT_SYMBOL(qcom_scm_lmh_dcvsh_available); + +int qcom_scm_lmh_profile_change(u32 profile_id) +{ + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_LMH, + .cmd = QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE, + .arginfo = QCOM_SCM_ARGS(1, QCOM_SCM_VAL), + .args[0] = profile_id, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + return qcom_scm_call(__scm->dev, &desc, NULL); +} +EXPORT_SYMBOL(qcom_scm_lmh_profile_change); + +int qcom_scm_lmh_dcvsh(u32 *payload, u32 payload_size, u64 limit_node, u32 node_id, u64 version) +{ + dma_addr_t payload_phys; + void *payload_buf; + + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_LMH, + .cmd = QCOM_SCM_LMH_LIMIT_DCVSH, + .arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_VAL, + QCOM_SCM_VAL, QCOM_SCM_VAL), + .args[1] = payload_size, + .args[2] = limit_node, + .args[3] = node_id, + .args[4] = version, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + payload_buf = dma_alloc_coherent(__scm->dev, payload_size, &payload_phys, GFP_KERNEL); + if (!payload_buf) + return -ENOMEM; + memcpy(payload_buf, payload, payload_size); + + desc.args[0] = payload_phys; + return qcom_scm_call(__scm->dev, &desc, NULL); +} +EXPORT_SYMBOL(qcom_scm_lmh_dcvsh); + static int qcom_scm_find_dload_address(struct device *dev, u64 *addr) { struct device_node *tcsr; diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index 632fe3142462..d92156ceb3ac 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -114,6 +114,10 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_SVC_HDCP 0x11 #define QCOM_SCM_HDCP_INVOKE 0x01 +#define QCOM_SCM_SVC_LMH 0x13 +#define QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE 0x01 +#define QCOM_SCM_LMH_LIMIT_DCVSH 0x10 + #define QCOM_SCM_SVC_SMMU_PROGRAM 0x15 #define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03 #define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02 diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index 0165824c5128..0c92197769e7 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -109,6 +109,12 @@ extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp); extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en); + +extern int qcom_scm_lmh_dcvsh(u32 *payload, u32 payload_size, u64 limit_node, + u32 node_id, u64 version); +extern int qcom_scm_lmh_profile_change(u32 profile_id); +extern bool qcom_scm_lmh_dcvsh_available(void); + #else #include <linux/errno.h> @@ -170,5 +176,12 @@ static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en) { return -ENODEV; } + +int qcom_scm_lmh_dcvsh(u32 *payload, u32 payload_size, u64 limit_node, + u32 node_id, u64 version) + { return -ENODEV; } +int qcom_scm_lmh_profile_change(u32 profile_id) { return -ENODEV; } + +bool qcom_scm_lmh_dcvsh_available(void) { return -ENODEV; } #endif #endif
Introduce SCM calls to access/configure limits management hardware(LMh). Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org> --- drivers/firmware/qcom_scm.c | 47 +++++++++++++++++++++++++++++++++++++ drivers/firmware/qcom_scm.h | 4 ++++ include/linux/qcom_scm.h | 13 ++++++++++ 3 files changed, 64 insertions(+)