| Message ID | 20210911163919.47173-1-angelogioacchino.delregno@somainline.org (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | [v2,1/2] drm/msm/dpu: Add a function to retrieve the current CTL status | expand |
On 11/09/2021 19:39, AngeloGioacchino Del Regno wrote: > Add a function that returns whether the requested CTL is active or not: > this will be used in a later commit to fix command mode panel issues. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 ++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 7 +++++++ > 2 files changed, 13 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > index 64740ddb983e..3b6fd73eb3a8 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > @@ -91,6 +91,11 @@ static inline void dpu_hw_ctl_trigger_start(struct dpu_hw_ctl *ctx) > DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1); > } > > +static inline bool dpu_hw_ctl_is_started(struct dpu_hw_ctl *ctx) > +{ > + return !!(DPU_REG_READ(&ctx->hw, CTL_START) & BIT(0)); > +} > + > static inline void dpu_hw_ctl_trigger_pending(struct dpu_hw_ctl *ctx) > { > trace_dpu_hw_ctl_trigger_prepare(ctx->pending_flush_mask, > @@ -579,6 +584,7 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, > ops->get_pending_flush = dpu_hw_ctl_get_pending_flush; > ops->get_flush_register = dpu_hw_ctl_get_flush_register; > ops->trigger_start = dpu_hw_ctl_trigger_start; > + ops->is_started = dpu_hw_ctl_is_started; > ops->trigger_pending = dpu_hw_ctl_trigger_pending; > ops->reset = dpu_hw_ctl_reset_control; > ops->wait_reset_status = dpu_hw_ctl_wait_reset_status; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > index 806c171e5df2..ac1544474022 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > @@ -61,6 +61,13 @@ struct dpu_hw_ctl_ops { > */ > void (*trigger_start)(struct dpu_hw_ctl *ctx); > > + /** > + * check if the ctl is started > + * @ctx : ctl path ctx pointer > + * @Return: true if started, false if stopped > + */ > + bool (*is_started)(struct dpu_hw_ctl *ctx); > + > /** > * kickoff prepare is in progress hw operation for sw > * controlled interfaces: DSI cmd mode and WB interface
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 64740ddb983e..3b6fd73eb3a8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -91,6 +91,11 @@ static inline void dpu_hw_ctl_trigger_start(struct dpu_hw_ctl *ctx) DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1); } +static inline bool dpu_hw_ctl_is_started(struct dpu_hw_ctl *ctx) +{ + return !!(DPU_REG_READ(&ctx->hw, CTL_START) & BIT(0)); +} + static inline void dpu_hw_ctl_trigger_pending(struct dpu_hw_ctl *ctx) { trace_dpu_hw_ctl_trigger_prepare(ctx->pending_flush_mask, @@ -579,6 +584,7 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, ops->get_pending_flush = dpu_hw_ctl_get_pending_flush; ops->get_flush_register = dpu_hw_ctl_get_flush_register; ops->trigger_start = dpu_hw_ctl_trigger_start; + ops->is_started = dpu_hw_ctl_is_started; ops->trigger_pending = dpu_hw_ctl_trigger_pending; ops->reset = dpu_hw_ctl_reset_control; ops->wait_reset_status = dpu_hw_ctl_wait_reset_status; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index 806c171e5df2..ac1544474022 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -61,6 +61,13 @@ struct dpu_hw_ctl_ops { */ void (*trigger_start)(struct dpu_hw_ctl *ctx); + /** + * check if the ctl is started + * @ctx : ctl path ctx pointer + * @Return: true if started, false if stopped + */ + bool (*is_started)(struct dpu_hw_ctl *ctx); + /** * kickoff prepare is in progress hw operation for sw * controlled interfaces: DSI cmd mode and WB interface
Add a function that returns whether the requested CTL is active or not: this will be used in a later commit to fix command mode panel issues. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 ++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 7 +++++++ 2 files changed, 13 insertions(+)