diff mbox series

[14/15] arm64: dts: qcom: sm8450: add cpufreq support

Message ID 20211201072915.3969178-15-vkoul@kernel.org (mailing list archive)
State Superseded
Headers show
Series arm64: dts: qcom: Add support for SM8450 SoC and QRD board | expand

Commit Message

Vinod Koul Dec. 1, 2021, 7:29 a.m. UTC 
From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>

The change adds a description of a SM8450 cpufreq-epss controller and
references to it from CPU nodes.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

Comments

Konrad Dybcio Dec. 1, 2021, 3:28 p.m. UTC | #1 
On 01.12.2021 08:29, Vinod Koul wrote:
> From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
>
> The change adds a description of a SM8450 cpufreq-epss controller and
> references to it from CPU nodes.
>
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
>  arch/arm64/boot/dts/qcom/sm8450.dtsi | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
>
[...]


>  
> +			cluster1 {
>  				core4 {
>  					cpu = <&CPU4>;
>  				};
> @@ -182,7 +192,9 @@ core5 {
>  				core6 {
>  					cpu = <&CPU6>;
>  				};
> +			};
>  
> +			cluster2 {
>  				core7 {
>  					cpu = <&CPU7>;
>  				};

Weren't DynamIQ-enabled SoCs supposed to be treated as single-cluster

from the Linux POV? Or has it changed again with the new chips?


[...]


Konrad
Vinod Koul Dec. 9, 2021, 7:11 a.m. UTC | #2 
On 01-12-21, 16:28, Konrad Dybcio wrote:
> 
> On 01.12.2021 08:29, Vinod Koul wrote:
> > From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> >
> > The change adds a description of a SM8450 cpufreq-epss controller and
> > references to it from CPU nodes.
> >
> > Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> >  arch/arm64/boot/dts/qcom/sm8450.dtsi | 27 +++++++++++++++++++++++++++
> >  1 file changed, 27 insertions(+)
> >
> [...]
> 
> 
> >  
> > +			cluster1 {
> >  				core4 {
> >  					cpu = <&CPU4>;
> >  				};
> > @@ -182,7 +192,9 @@ core5 {
> >  				core6 {
> >  					cpu = <&CPU6>;
> >  				};
> > +			};
> >  
> > +			cluster2 {
> >  				core7 {
> >  					cpu = <&CPU7>;
> >  				};
> 
> Weren't DynamIQ-enabled SoCs supposed to be treated as single-cluster
> 
> from the Linux POV? Or has it changed again with the new chips?

I discussed with Bjorn and yes we should have a single cluster for this.
will fix
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 8f0819df8039..29c5abcfa074 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -45,6 +45,7 @@  CPU0: cpu@0 {
 			next-level-cache = <&L2_0>;
 			power-domains = <&CPU_PD0>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			L2_0: l2-cache {
 			      compatible = "cache";
 			      next-level-cache = <&L3_0>;
@@ -62,6 +63,7 @@  CPU1: cpu@100 {
 			next-level-cache = <&L2_100>;
 			power-domains = <&CPU_PD1>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			L2_100: l2-cache {
 			      compatible = "cache";
 			      next-level-cache = <&L3_0>;
@@ -76,6 +78,7 @@  CPU2: cpu@200 {
 			next-level-cache = <&L2_200>;
 			power-domains = <&CPU_PD2>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			L2_200: l2-cache {
 			      compatible = "cache";
 			      next-level-cache = <&L3_0>;
@@ -90,6 +93,7 @@  CPU3: cpu@300 {
 			next-level-cache = <&L2_300>;
 			power-domains = <&CPU_PD3>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			L2_300: l2-cache {
 			      compatible = "cache";
 			      next-level-cache = <&L3_0>;
@@ -104,6 +108,7 @@  CPU4: cpu@400 {
 			next-level-cache = <&L2_400>;
 			power-domains = <&CPU_PD4>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 1>;
 			L2_400: l2-cache {
 			      compatible = "cache";
 			      next-level-cache = <&L3_0>;
@@ -118,6 +123,7 @@  CPU5: cpu@500 {
 			next-level-cache = <&L2_500>;
 			power-domains = <&CPU_PD5>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 1>;
 			L2_500: l2-cache {
 			      compatible = "cache";
 			      next-level-cache = <&L3_0>;
@@ -133,6 +139,7 @@  CPU6: cpu@600 {
 			next-level-cache = <&L2_600>;
 			power-domains = <&CPU_PD6>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 1>;
 			L2_600: l2-cache {
 			      compatible = "cache";
 			      next-level-cache = <&L3_0>;
@@ -147,6 +154,7 @@  CPU7: cpu@700 {
 			next-level-cache = <&L2_700>;
 			power-domains = <&CPU_PD7>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 2>;
 			L2_700: l2-cache {
 			      compatible = "cache";
 			      next-level-cache = <&L3_0>;
@@ -170,7 +178,9 @@  core2 {
 				core3 {
 					cpu = <&CPU3>;
 				};
+			};
 
+			cluster1 {
 				core4 {
 					cpu = <&CPU4>;
 				};
@@ -182,7 +192,9 @@  core5 {
 				core6 {
 					cpu = <&CPU6>;
 				};
+			};
 
+			cluster2 {
 				core7 {
 					cpu = <&CPU7>;
 				};
@@ -943,6 +955,21 @@  rpmhpd_opp_turbo_l1: opp10 {
 
 		};
 
+		cpufreq_hw: cpufreq@17d91000 {
+			compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
+			reg = <0 0x17d91000 0 0x1000>,
+			      <0 0x17d92000 0 0x1000>,
+			      <0 0x17d93000 0 0x1000>;
+			reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+			clock-names = "xo", "alternate";
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
+			#freq-domain-cells = <1>;
+		};
+
 		gem_noc: interconnect@19100000 {
 			reg = <0 0x19100000 0 0xbb800>;
 			compatible = "qcom,sm8450-gem-noc";