| Message ID | 20211201072915.3969178-16-vkoul@kernel.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: dts: qcom: Add support for SM8450 SoC and QRD board | expand |
On 01.12.2021 08:29, Vinod Koul wrote: > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > Add device tree nodes for two i2c blocks: i2c13 and i2c14. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Signed-off-by: Vinod Koul <vkoul@kernel.org> > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 64 ++++++++++++++++++++++++++++ > 1 file changed, 64 insertions(+) > [...] > config_noc: interconnect@1500000 { > compatible = "qcom,sm8450-config-noc"; > reg = <0 0x01500000 0 0x1c000>; > @@ -687,6 +725,32 @@ tlmm: pinctrl@f100000 { > gpio-ranges = <&tlmm 0 0 211>; > wakeup-parent = <&pdc>; > > + qup_i2c13_default_state: qup-i2c13-default-state { > + mux { > + pins = "gpio48", "gpio49"; > + function = "qup13"; > + }; > + > + config { > + pins = "gpio48", "gpio49"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + }; > + This should be collapsed into: qup_i2c13_default_state: qup-i2c13-default-state { pins = "..." function = "..." drive-strength = <2> bias-pull-up; }; And the same goes for the rest of the pins. [...] Konrad
On 01-12-21, 16:30, Konrad Dybcio wrote: > > On 01.12.2021 08:29, Vinod Koul wrote: > > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > > > Add device tree nodes for two i2c blocks: i2c13 and i2c14. > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > Signed-off-by: Vinod Koul <vkoul@kernel.org> > > --- > > arch/arm64/boot/dts/qcom/sm8450.dtsi | 64 ++++++++++++++++++++++++++++ > > 1 file changed, 64 insertions(+) > > > [...] > > > > config_noc: interconnect@1500000 { > > compatible = "qcom,sm8450-config-noc"; > > reg = <0 0x01500000 0 0x1c000>; > > @@ -687,6 +725,32 @@ tlmm: pinctrl@f100000 { > > gpio-ranges = <&tlmm 0 0 211>; > > wakeup-parent = <&pdc>; > > > > + qup_i2c13_default_state: qup-i2c13-default-state { > > + mux { > > + pins = "gpio48", "gpio49"; > > + function = "qup13"; > > + }; > > + > > + config { > > + pins = "gpio48", "gpio49"; > > + drive-strength = <2>; > > + bias-pull-up; > > + }; > > + }; > > + > > This should be collapsed into: > > > qup_i2c13_default_state: qup-i2c13-default-state { > > pins = "..." > > function = "..." > > drive-strength = <2> > > bias-pull-up; > > }; > > > And the same goes for the rest of the pins. Yeah that looks neater and done that now
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 29c5abcfa074..40c739b842ac 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -587,6 +587,44 @@ uart7: serial@99c000 { }; }; + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a94000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c13_default_state>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a98000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c14_default_state>; + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + config_noc: interconnect@1500000 { compatible = "qcom,sm8450-config-noc"; reg = <0 0x01500000 0 0x1c000>; @@ -687,6 +725,32 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 211>; wakeup-parent = <&pdc>; + qup_i2c13_default_state: qup-i2c13-default-state { + mux { + pins = "gpio48", "gpio49"; + function = "qup13"; + }; + + config { + pins = "gpio48", "gpio49"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qup_i2c14_default_state: qup-i2c14-default-state { + mux { + pins = "gpio52", "gpio53"; + function = "qup14"; + }; + + config { + pins = "gpio49", "gpio50"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup_uart7_default_state: qup-uart3-default-state { rx { pins = "gpio26";