| Message ID | 20211201072915.3969178-4-vkoul@kernel.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: dts: qcom: Add support for SM8450 SoC and QRD board | expand |
On Tue 30 Nov 23:29 PST 2021, Vinod Koul wrote: > Add tlmm node found in SM8450 SoC and uart pin configuration > > Signed-off-by: Vinod Koul <vkoul@kernel.org> > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 29 ++++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index d838283bde4b..f0b9e80238a2 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -343,6 +343,8 @@ uart7: serial@99c000 { > reg = <0 0x0099c000 0 0x4000>; > clock-names = "se"; > clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_uart7_default_state>; > interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; > #address-cells = <1>; > #size-cells = <0>; > @@ -366,6 +368,33 @@ pdc: interrupt-controller@b220000 { > interrupt-controller; > }; > > + tlmm: pinctrl@f100000 { > + compatible = "qcom,sm8450-tlmm"; > + reg = <0 0x0f100000 0 0x300000>; > + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&tlmm 0 0 211>; > + wakeup-parent = <&pdc>; > + > + qup_uart7_default_state: qup-uart3-default-state { There's a '3' in the node name. Loos good otherwise. Thanks, Bjorn > + rx { > + pins = "gpio26"; > + function = "qup7"; > + drive-strength = <2>; > + bias-disable; > + }; > + tx { > + pins = "gpio27"; > + function = "qup7"; > + drive-strength = <2>; > + bias-disable; > + }; > + }; > + }; > + > intc: interrupt-controller@17100000 { > compatible = "arm,gic-v3"; > #interrupt-cells = <3>; > -- > 2.31.1 >
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index d838283bde4b..f0b9e80238a2 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -343,6 +343,8 @@ uart7: serial@99c000 { reg = <0 0x0099c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart7_default_state>; interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -366,6 +368,33 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; + tlmm: pinctrl@f100000 { + compatible = "qcom,sm8450-tlmm"; + reg = <0 0x0f100000 0 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 211>; + wakeup-parent = <&pdc>; + + qup_uart7_default_state: qup-uart3-default-state { + rx { + pins = "gpio26"; + function = "qup7"; + drive-strength = <2>; + bias-disable; + }; + tx { + pins = "gpio27"; + function = "qup7"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + intc: interrupt-controller@17100000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>;
Add tlmm node found in SM8450 SoC and uart pin configuration Signed-off-by: Vinod Koul <vkoul@kernel.org> --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 29 ++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)