From patchwork Thu Dec 9 10:35:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12666369 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30DCCC433FE for ; Thu, 9 Dec 2021 10:36:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235352AbhLIKji (ORCPT ); Thu, 9 Dec 2021 05:39:38 -0500 Received: from sin.source.kernel.org ([145.40.73.55]:54434 "EHLO sin.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235286AbhLIKj3 (ORCPT ); Thu, 9 Dec 2021 05:39:29 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id D4492CE2576; Thu, 9 Dec 2021 10:35:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 301B4C341C3; Thu, 9 Dec 2021 10:35:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639046153; bh=emf2Yi1eiIxyrS0RiasyqhBYmlqekS8lTjt0MK+WlVE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kyeISIHMzIkognjgqBabZSmwMiuLJs1DHt+hZmMVlBDxrO6VLEtQRuDkrbCEXLFOe 1C5ce6G8ryXlc30rRsqbm18jW0mwDEhFuaw1B7shlHCIHlWCQggWL8PQ47jfkziq+A /1nS0mbrLNGRnHllLmxR0ViXl+bv4zrwd4UFlttahhArp4p2yMSIKr0ZGomx4qiJY5 jsj13tiJ+fnJswJFiD9aqPM20T/YJhKx87nMhl/c9isUweLQDAkZ2dwTH0jZnxJIPt HKFxqLmH+gnlHkh6t6tRa4jjXD7owy1qC+Zfz3TnUFCw3iFxo9Kk6RbT+Xfu8B2StH 4V77+s8fEDeAg== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vladimir Zapolskiy , Andy Gross , Rob Herring , Konrad Dybcio , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Subject: [PATCH v2 12/13] arm64: dts: qcom: sm8450: add cpufreq support Date: Thu, 9 Dec 2021 16:05:04 +0530 Message-Id: <20211209103505.197453-13-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211209103505.197453-1-vkoul@kernel.org> References: <20211209103505.197453-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Vladimir Zapolskiy The change adds a description of a SM8450 cpufreq-epss controller and references to it from CPU nodes. Signed-off-by: Vladimir Zapolskiy Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index f303e12dbfb7..94bc8b352547 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -45,6 +45,7 @@ CPU0: cpu@0 { next-level-cache = <&L2_0>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -62,6 +63,7 @@ CPU1: cpu@100 { next-level-cache = <&L2_100>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -76,6 +78,7 @@ CPU2: cpu@200 { next-level-cache = <&L2_200>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -90,6 +93,7 @@ CPU3: cpu@300 { next-level-cache = <&L2_300>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -104,6 +108,7 @@ CPU4: cpu@400 { next-level-cache = <&L2_400>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -118,6 +123,7 @@ CPU5: cpu@500 { next-level-cache = <&L2_500>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -133,6 +139,7 @@ CPU6: cpu@600 { next-level-cache = <&L2_600>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -147,6 +154,7 @@ CPU7: cpu@700 { next-level-cache = <&L2_700>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 2>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -942,6 +950,21 @@ rpmhpd_opp_turbo_l1: opp10 { }; + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0 0x17d91000 0 0x1000>, + <0 0x17d92000 0 0x1000>, + <0 0x17d93000 0 0x1000>; + reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + interrupts = , + , + ; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; + #freq-domain-cells = <1>; + }; + gem_noc: interconnect@19100000 { compatible = "qcom,sm8450-gem-noc"; reg = <0 0x19100000 0 0xbb800>;