| Message ID | 20220621195512.1760362-1-robimarko@gmail.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | [v4,1/3] phy: qcom-qmp-pcie: make pipe clock rate configurable | expand |
On Tue, 21 Jun 2022 at 22:55, Robert Marko <robimarko@gmail.com> wrote: > > IPQ8074 Gen3 PCIe PHY uses 250MHz as the pipe clock rate instead of 125MHz > like every other PCIe QMP PHY does, so make it configurable as part of the > qmp_phy_cfg. > > Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > Changes in v4: > * Set 125MHz as the default if not set in qmp_phy_cfg > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 14 ++++++++++++-- > 1 file changed, 12 insertions(+), 2 deletions(-) >
On 21-06-22, 21:55, Robert Marko wrote: > IPQ8074 Gen3 PCIe PHY uses 250MHz as the pipe clock rate instead of 125MHz > like every other PCIe QMP PHY does, so make it configurable as part of the > qmp_phy_cfg. Applied, thanks
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index b2cd0cf965d8..66be854fe7f3 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1284,6 +1284,9 @@ struct qmp_phy_cfg { /* true, if PHY has secondary tx/rx lanes to be configured */ bool is_dual_lane_phy; + + /* QMP PHY pipe clock interface rate */ + unsigned long pipe_clock_rate; }; /** @@ -2121,8 +2124,15 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) init.ops = &clk_fixed_rate_ops; - /* controllers using QMP phys use 125MHz pipe clock interface */ - fixed->fixed_rate = 125000000; + /* + * Controllers using QMP PHY-s use 125MHz pipe clock interface + * unless other frequency is specified in the PHY config. + */ + if (qmp->phys[0]->cfg->pipe_clock_rate) + fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate; + else + fixed->fixed_rate = 125000000; + fixed->hw.init = &init; ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
IPQ8074 Gen3 PCIe PHY uses 250MHz as the pipe clock rate instead of 125MHz like every other PCIe QMP PHY does, so make it configurable as part of the qmp_phy_cfg. Signed-off-by: Robert Marko <robimarko@gmail.com> --- Changes in v4: * Set 125MHz as the default if not set in qmp_phy_cfg --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-)