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[98.239.145.235]) by smtp.gmail.com with ESMTPSA id d124-20020a379b82000000b006a6ae9150fesm18412531qke.41.2022.06.23.07.28.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 07:28:56 -0700 (PDT) From: Brian Masney To: bjorn.andersson@linaro.org, linux-arm-msm@vger.kernel.org Cc: agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.com Subject: [PATCH] clk: qcom: sc8280xp: add parent to gcc_ufs_phy_axi_clk for sa8540p Date: Thu, 23 Jun 2022 10:28:37 -0400 Message-Id: <20220623142837.3140680-1-bmasney@redhat.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The sa8540p automotive board has the same SOC as the sc8280xp. In order to get the first UFS controller working on the sa8540p, GCC_UFS_REF_CLKREF_CLK needs to be setup as a parent to GCC_UFS_PHY_AXI_CLK. This clock name came from the DTS for the downstream MSM 5.4 kernel sources for the sa8540p. It also references GCC_UFS_CARD_CLKREF_CLK, however that wasn't needed to get the first UFS controller working. Signed-off-by: Brian Masney --- I originally added this under GCC_UFS_PHY_PHY_AUX_CLK since that's what's in the downstream DTS. I was getting errors about GCC_UFS_PHY_AXI_CLK being stuck at off so I moved it there. Also I don't have access to any documentation for this board so I'm hoping that someone with docs access can verify that this is the appropriate place to put this. drivers/clk/qcom/gcc-sc8280xp.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c index 4b894442fdf5..4639b50da418 100644 --- a/drivers/clk/qcom/gcc-sc8280xp.c +++ b/drivers/clk/qcom/gcc-sc8280xp.c @@ -5685,6 +5685,19 @@ static struct clk_branch gcc_ufs_phy_ahb_clk = { }, }; +static struct clk_branch gcc_ufs_ref_clkref_clk = { + .halt_reg = 0x8c058, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8c058, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_ufs_ref_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_ufs_phy_axi_clk = { .halt_reg = 0x77010, .halt_check = BRANCH_HALT_VOTED, @@ -5696,6 +5709,7 @@ static struct clk_branch gcc_ufs_phy_axi_clk = { .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_axi_clk", .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_ref_clkref_clk.clkr.hw, &gcc_ufs_phy_axi_clk_src.clkr.hw, }, .num_parents = 1, @@ -5899,19 +5913,6 @@ static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { }, }; -static struct clk_branch gcc_ufs_ref_clkref_clk = { - .halt_reg = 0x8c058, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c058, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_ufs_ref_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_usb2_hs0_clkref_clk = { .halt_reg = 0x8c044, .halt_check = BRANCH_HALT,