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[88.112.131.206]) by smtp.gmail.com with ESMTPSA id w10-20020a2e9bca000000b0025a65ed7aa4sm262345ljj.51.2022.06.24.04.59.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jun 2022 04:59:40 -0700 (PDT) From: Vladimir Zapolskiy To: Bjorn Andersson Cc: Andy Gross , Rob Herring , Stephen Boyd , Michael Turquette , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v8 2/7] arm64: dts: qcom: sm8450: Add description of camera clock controller Date: Fri, 24 Jun 2022 14:59:17 +0300 Message-Id: <20220624115917.2524868-3-vladimir.zapolskiy@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220624115917.2524868-1-vladimir.zapolskiy@linaro.org> References: <20220624115917.2524868-1-vladimir.zapolskiy@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add description of QCOM SM8450 camera clock controller. Signed-off-by: Vladimir Zapolskiy --- Changes from v7 to v8: * rebased on top of v5.19-rc2, * minor improvement to the commit message. Changes from v6 to v7: * rebased on top of v5.19-rc1. Changes from v5 to v6: * rebased on top of linux-next. Changes from v3 to v5: * none. Changes from v2 to v3: * account a renamed header file. Changes from v1 to v2: * disabled camcc device tree node by default. arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 7d08fad76371..fad813a21df5 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -2288,6 +2289,25 @@ IPCC_MPROC_SIGNAL_GLINK_QMP }; }; + camcc: clock-controller@ade0000 { + compatible = "qcom,sm8450-camcc"; + reg = <0 0x0ade0000 0 0x20000>; + status = "disabled"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "iface", + "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk"; + power-domains = <&rpmhpd SM8450_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8450-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;