From patchwork Fri Aug 12 08:27:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 12942029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05DCAC282E7 for ; Fri, 12 Aug 2022 08:28:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237024AbiHLI2L (ORCPT ); Fri, 12 Aug 2022 04:28:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237442AbiHLI2J (ORCPT ); Fri, 12 Aug 2022 04:28:09 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA36CA8944 for ; Fri, 12 Aug 2022 01:28:05 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id kb8so814290ejc.4 for ; Fri, 12 Aug 2022 01:28:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=YtXfWrLU1BZPc0rfRaWUKHk31M+JfVKZR86pVQ/2Egk=; b=UzrkX0IxhkIOXzUyXy0xY8Pll/YDDoDIG7iHl3U+UObYWU6CeqAZ3hcuERe48Eg4qj cV2/S/42bnyKsJY1Si7MlZEp5/u4Wrf87aCqSvdBIulw5gLv/3RRZ3uJZYOiJofkZ9Y2 KEhuG+yWXpjouBuYLYdfniUlwiOWgmCv6E00nCK+SPNXnWJ/sdthIkFtZTnhRkuzTBJz n0MPn7fLsJU7m2vNk/p07lG0AK1qejrV3+dRBJxRmDPU38AO3Ifuu7uVk4JARAkrruB8 3SBPXHwiQIkGe0dhUtIBBZWwFvkzYroUPIJcpzxCqd/9r13jF+8wFglO+UmMWtrGYEz9 kvKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=YtXfWrLU1BZPc0rfRaWUKHk31M+JfVKZR86pVQ/2Egk=; b=QZLTOATr2qXPhFKZOh6EYlCA11UjbhQJKqPjjEZ2kaonDnbF8NZ9sfNh0h3Wn+mGkt buZAczEA/r6eYE+W1LIHA8tKuOcuN27EehJnCJ9GiXKxm0W1bv5LiBfiY6UHq1fJfD+H 4WMza6BwLXKSbytU41C3GXOD2FmmoV6tnklQTqbhYw/18Iog1hkBazxhvdms4C/fsiaM czQJ/pQQvUFxY3So/+Q1wddRO65vHpfCdCE2CKVl6oe/6wqhT7OOFrOXkSo2Bm+PLhXh 4xAOtMj3GgJz2D4ap3+sARkn0s8O4KD7KvJIBt5et5p06grDMacxOvYGhByNRM127KZ5 zZ1g== X-Gm-Message-State: ACgBeo3mHSIrspQvs1P2uGg4LVWdXrlKpnMJV41gIW+WtnlBUS/g2kLW OPSauUxyxIFlvOROqSpo3MBHxBQMklfKCg== X-Google-Smtp-Source: AA6agR7S1IBFsA6x0Q1AZL0/ULItvXSqg/Ku54We6vkcsLprZSGLimKyiRcd6EL7RotjPHmIr9Qkow== X-Received: by 2002:a17:907:842:b0:731:3310:4187 with SMTP id ww2-20020a170907084200b0073133104187mr1879973ejb.578.1660292884039; Fri, 12 Aug 2022 01:28:04 -0700 (PDT) Received: from otso.arnhem.chello.nl (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id y6-20020a056402134600b0043cf1c6bb10sm971326edw.25.2022.08.12.01.28.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Aug 2022 01:28:03 -0700 (PDT) From: Luca Weiss To: linux-arm-msm@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Luca Weiss , Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] arm64: dts: qcom: sm6350: Add GPI DMA nodes Date: Fri, 12 Aug 2022 10:27:21 +0200 Message-Id: <20220812082721.1125759-4-luca.weiss@fairphone.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220812082721.1125759-1-luca.weiss@fairphone.com> References: <20220812082721.1125759-1-luca.weiss@fairphone.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add nodes for the gpi_dma0 and gpi_dma1 which are (optionally) used for various i2c busses based on the qup firmware configuration. Signed-off-by: Luca Weiss Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 59 ++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 76f14d54ae1c..5de6eb26f904 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -517,6 +518,26 @@ opp-384000000 { }; }; + gpi_dma0: dma-controller@800000 { + compatible = "qcom,sm6350-gpi-dma"; + reg = <0 0x00800000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + dma-channels = <10>; + dma-channel-mask = <0x1f>; + iommus = <&apps_smmu 0x56 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x8c0000 0x0 0x2000>; @@ -537,6 +558,9 @@ i2c0: i2c@880000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c0_default>; interrupts = ; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -550,12 +574,35 @@ i2c2: i2c@888000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c2_default>; interrupts = ; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; + gpi_dma1: dma-controller@900000 { + compatible = "qcom,sm6350-gpi-dma"; + reg = <0 0x00900000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + dma-channels = <10>; + dma-channel-mask = <0x3f>; + iommus = <&apps_smmu 0x4d6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_1: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x9c0000 0x0 0x2000>; @@ -576,6 +623,9 @@ i2c6: i2c@980000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c6_default>; interrupts = ; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -589,6 +639,9 @@ i2c7: i2c@984000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c7_default>; interrupts = ; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -602,6 +655,9 @@ i2c8: i2c@988000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c8_default>; interrupts = ; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -626,6 +682,9 @@ i2c10: i2c@990000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c10_default>; interrupts = ; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled";