| Message ID | 20220825163755.683843-1-bmasney@redhat.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2] arm64: dts: qcom: sc8280xp: correct ref_aux clock for ufs_mem_phy | expand |
On Thu, Aug 25, 2022 at 12:37:55PM -0400, Brian Masney wrote: > The first UFS host controller fails to start on the SA8540P automotive > board (QDrive3) due to the following errors: > > ufshcd-qcom 1d84000.ufs: ufshcd_query_flag: Sending flag query for idn 18 failed, err = 253 > ufshcd-qcom 1d84000.ufs: ufshcd_query_flag: Sending flag query for idn 18 failed, err = 253 > ufshcd-qcom 1d84000.ufs: ufshcd_query_flag: Sending flag query for idn 18 failed, err = 253 > ufshcd-qcom 1d84000.ufs: ufshcd_query_flag_retry: query attribute, opcode 5, idn 18, failed > with error 253 after 3 retries > > The system eventually fails to boot with the warning: > > gcc_ufs_phy_axi_clk status stuck at 'off' > > This issue can be worked around by adding clk_ignore_unused to the > kernel command line since the system firmware sets up this clock for us. > > Let's fix this issue by updating the ref_aux clock on ufs_mem_phy. Note > that the downstream MSM 5.4 sources list this as ref_clk_parent. With > this patch, the SA8540P is able to be booted without clk_ignore_unused. > > Signed-off-by: Brian Masney <bmasney@redhat.com> > Fixes: 152d1faf1e2f3 ("arm64: dts: qcom: add SC8280XP platform") > --- > v1 of this patch can be found at > https://lore.kernel.org/lkml/20220623142837.3140680-1-bmasney@redhat.com/T/#u > > Note that there's also a similar issue with the second UFS controller > (ufs_card_hc) since it separately fails with: > > ufshcd-qcom 1da4000.ufs: Controller enable failed > ufshcd-qcom 1da4000.ufs: link startup failed 1 > ... > gcc_ufs_card_axi_clk status stuck at 'off' > > We are currently disabling the second UFS host controller (ufs_card_hc) in > our DTS at the moment. I'm still looking through the downstream code to > try to track this particular issue down. > > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > index 49ea8b5612fc..4117ec0ffefc 100644 > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > @@ -892,7 +892,7 @@ ufs_mem_phy: phy@1d87000 { > clock-names = "ref", > "ref_aux"; > clocks = <&rpmhcc RPMH_CXO_CLK>, > - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; > + <&gcc GCC_UFS_REF_CLKREF_CLK>; I would expect that "ref" was going to be GCC_UFS_REF_CLKREF_CLK and "ref_aux" would remain PHY_AUX. But the mapping here is not clear to me. But does that work for you? (i.e. clocks = <CLKREF>, <PHY_AUX>) Regards, Bjorn > > resets = <&ufs_mem_hc 0>; > reset-names = "ufsphy"; > -- > 2.37.1 >
On Mon, Aug 29, 2022 at 05:28:26PM -0500, Bjorn Andersson wrote: > On Thu, Aug 25, 2022 at 12:37:55PM -0400, Brian Masney wrote: > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > > index 49ea8b5612fc..4117ec0ffefc 100644 > > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > > @@ -892,7 +892,7 @@ ufs_mem_phy: phy@1d87000 { > > clock-names = "ref", > > "ref_aux"; > > clocks = <&rpmhcc RPMH_CXO_CLK>, > > - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; > > + <&gcc GCC_UFS_REF_CLKREF_CLK>; > > I would expect that "ref" was going to be GCC_UFS_REF_CLKREF_CLK and > "ref_aux" would remain PHY_AUX. But the mapping here is not clear to me. > > But does that work for you? (i.e. clocks = <CLKREF>, <PHY_AUX>) Yes, that works for me. I'll send out a new revision shortly. Brian
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 49ea8b5612fc..4117ec0ffefc 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -892,7 +892,7 @@ ufs_mem_phy: phy@1d87000 { clock-names = "ref", "ref_aux"; clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + <&gcc GCC_UFS_REF_CLKREF_CLK>; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy";
The first UFS host controller fails to start on the SA8540P automotive board (QDrive3) due to the following errors: ufshcd-qcom 1d84000.ufs: ufshcd_query_flag: Sending flag query for idn 18 failed, err = 253 ufshcd-qcom 1d84000.ufs: ufshcd_query_flag: Sending flag query for idn 18 failed, err = 253 ufshcd-qcom 1d84000.ufs: ufshcd_query_flag: Sending flag query for idn 18 failed, err = 253 ufshcd-qcom 1d84000.ufs: ufshcd_query_flag_retry: query attribute, opcode 5, idn 18, failed with error 253 after 3 retries The system eventually fails to boot with the warning: gcc_ufs_phy_axi_clk status stuck at 'off' This issue can be worked around by adding clk_ignore_unused to the kernel command line since the system firmware sets up this clock for us. Let's fix this issue by updating the ref_aux clock on ufs_mem_phy. Note that the downstream MSM 5.4 sources list this as ref_clk_parent. With this patch, the SA8540P is able to be booted without clk_ignore_unused. Signed-off-by: Brian Masney <bmasney@redhat.com> Fixes: 152d1faf1e2f3 ("arm64: dts: qcom: add SC8280XP platform") --- v1 of this patch can be found at https://lore.kernel.org/lkml/20220623142837.3140680-1-bmasney@redhat.com/T/#u Note that there's also a similar issue with the second UFS controller (ufs_card_hc) since it separately fails with: ufshcd-qcom 1da4000.ufs: Controller enable failed ufshcd-qcom 1da4000.ufs: link startup failed 1 ... gcc_ufs_card_axi_clk status stuck at 'off' We are currently disabling the second UFS host controller (ufs_card_hc) in our DTS at the moment. I'm still looking through the downstream code to try to track this particular issue down. arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)