diff mbox series

[1/3] ARM: dts: qcom-msm8660: Add GSBI1 SPI bus

Message ID 20220913132846.305716-1-linus.walleij@linaro.org (mailing list archive)
State Accepted, archived
Commit affa747d36aa81b2285fe0221e2624b0afaa3482
Headers show
Series [1/3] ARM: dts: qcom-msm8660: Add GSBI1 SPI bus | expand

Commit Message

Linus Walleij Sept. 13, 2022, 1:28 p.m. UTC
GSBI1 can be used to enable an external SPI bus on e.g. the
APQ8060. On the DragonBoard APQ8060 this SPI bus is used to
talk to the LCD display.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 arch/arm/boot/dts/qcom-msm8660.dtsi | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

Comments

Bjorn Andersson Sept. 13, 2022, 3:17 p.m. UTC | #1
On Tue, 13 Sep 2022 15:28:44 +0200, Linus Walleij wrote:
> GSBI1 can be used to enable an external SPI bus on e.g. the
> APQ8060. On the DragonBoard APQ8060 this SPI bus is used to
> talk to the LCD display.
> 
> 

Applied, thanks!

[1/3] ARM: dts: qcom-msm8660: Add GSBI1 SPI bus
      commit: affa747d36aa81b2285fe0221e2624b0afaa3482
[2/3] ARM: dts: qcom-msm8660: Add GSBI3 I2C bus
      commit: 77012a11c36e4609f2c0e0ff0bf215a8448d9033
[3/3] ARM: dts: qcom: Add TMA340 to APQ8060 DragonBoard
      commit: 2aac1179717d2bf7ed2747a823c104c918d37a80

Best regards,
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 63a501c63cf8..5640c02db852 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -131,6 +131,31 @@  gcc: clock-controller@900000 {
 			reg = <0x900000 0x4000>;
 		};
 
+		gsbi1: gsbi@16000000 {
+			compatible = "qcom,gsbi-v1.0.0";
+			cell-index = <12>;
+			reg = <0x16000000 0x100>;
+			clocks = <&gcc GSBI1_H_CLK>;
+			clock-names = "iface";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			status = "disabled";
+
+			syscon-tcsr = <&tcsr>;
+
+			gsbi1_spi: spi@16080000 {
+				compatible = "qcom,spi-qup-v1.1.1";
+				reg = <0x16080000 0x1000>;
+				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
+				clock-names = "core", "iface";
+				status = "disabled";
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
 		gsbi6: gsbi@16500000 {
 			compatible = "qcom,gsbi-v1.0.0";
 			cell-index = <12>;