From patchwork Wed Sep 28 09:14:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 12991915 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D859C32771 for ; Wed, 28 Sep 2022 09:15:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233535AbiI1JPY (ORCPT ); Wed, 28 Sep 2022 05:15:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233555AbiI1JPC (ORCPT ); Wed, 28 Sep 2022 05:15:02 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 901752316B for ; Wed, 28 Sep 2022 02:15:00 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id v28so5935279wrd.3 for ; Wed, 28 Sep 2022 02:15:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date; bh=Nps3ANTgE3seawbM5+PmTIn4OgiLjhxFHyf2GdOQ0aw=; b=lXtkUfmiU2FMJsUXOQ9XIdxJHNUBtovE3ktBFxkBzOg8PZznXCoQVdMUhJJVcYLP+E oLO6Fct/aCQrpTXIipnYA1ZrnUEPUyH0psrB3LZqwhSdjIjTOy7wXi0ZsLoKCHXlHQRa LKxSmQux1wf46YRXkN4/B7U/c7VGTXmFKf7pFKMWOy6lstY5rC6cbrNUAKIHCIWrGnrV P10sPlCeHv62tjFzAAGXlL8LGob4D3AxQY04CqX5/3tQfSb6Y0B9p1sm+6JWpkI4N9MA Sx0giQMbNdWfOQe6Uq0XkJUEpl6Qk2SgUGqGy+5BvJgo6nSw6BMCHZSCbTPk2cSvMiqs yaJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date; bh=Nps3ANTgE3seawbM5+PmTIn4OgiLjhxFHyf2GdOQ0aw=; b=2D9hTkt9WwUgZcnLr5WNnwhqV1zht1bH9f1LiV4HddKG8pd1jQvxt1rVAUlNuI1lze NoNaRSqbeTztOkmawhQ6rVitvN9TzZTmGxk2tJP+nY3BEqxHu7ddQwmNSrrrBcMK6+NU 36/H/5MjIAWkvdJHuMpbZZxKcrr+1l3FDmv2y/UJOFZfRo1kKNTOrNwEZJoYEtlsFUb6 F2SrWfu4vIbMDZOJ7UOUCNZBVSw/ds+aC4TqSHkuidzppFoW7V3hM7fA3b/PuDhYo8sr 2+/w+LmpwEPOm+VREv8e0LTSnlcAarQfi7vtltei6qHAaT2D5M0K55179gguj4LZYPYW COCA== X-Gm-Message-State: ACrzQf2C5fkZXWIhzmdjhTbGel/QtYbFHZmDMVBTM34meN78rU5mb32w XevaxGcAghRrw4LURAQur3puaw== X-Google-Smtp-Source: AMsMyM5/GiiOcSG8h4Q42kXYkm+cp1fWvkF4ICXjgnEHrrmPrXmpPhk8X6qMZA4gaaAVzUStl0KkDQ== X-Received: by 2002:adf:efc6:0:b0:22c:c6cc:87dc with SMTP id i6-20020adfefc6000000b0022cc6cc87dcmr2042704wrp.522.1664356499019; Wed, 28 Sep 2022 02:14:59 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id p2-20020a5d6382000000b0022a53fe201fsm2420016wru.68.2022.09.28.02.14.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Sep 2022 02:14:58 -0700 (PDT) From: Neil Armstrong Date: Wed, 28 Sep 2022 09:14:57 +0000 Subject: [PATCH v1 7/7] arm: dts: qcom: mdm9615: remove useless amba subnode MIME-Version: 1.0 Message-Id: <20220928-mdm9615-dt-schema-fixes-v1-7-b6e63a7df1e8@linaro.org> References: <20220928-mdm9615-dt-schema-fixes-v1-0-b6e63a7df1e8@linaro.org> In-Reply-To: <20220928-mdm9615-dt-schema-fixes-v1-0-b6e63a7df1e8@linaro.org> To: Andy Gross , Krzysztof Kozlowski , Bjorn Andersson , Rob Herring , Konrad Dybcio Cc: devicetree@vger.kernel.org, Neil Armstrong , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org X-Mailer: b4 0.10.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Since amba node type has been deprecated, remove this subnode and move the mmc nodes in the main soc node. Signed-off-by: Neil Armstrong diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index d8723bd3fedb..1db822db7702 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -314,49 +314,43 @@ sdcc2bam: dma-controller@12142000{ qcom,ee = <0>; }; - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - sdcc1: mmc@12180000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12180000 0x2000>; - interrupts = ; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <48000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; - dma-names = "tx", "rx"; - assigned-clocks = <&gcc SDC1_CLK>; - assigned-clock-rates = <400000>; - }; + sdcc1: mmc@12180000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12180000 0x2000>; + interrupts = ; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + assigned-clocks = <&gcc SDC1_CLK>; + assigned-clock-rates = <400000>; + }; - sdcc2: mmc@12140000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12140000 0x2000>; - interrupts = ; - clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <48000000>; - no-1-8-v; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc2bam 2>, <&sdcc2bam 1>; - dma-names = "tx", "rx"; - assigned-clocks = <&gcc SDC2_CLK>; - assigned-clock-rates = <400000>; - }; + sdcc2: mmc@12140000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12140000 0x2000>; + interrupts = ; + clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <48000000>; + no-1-8-v; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc2bam 2>, <&sdcc2bam 1>; + dma-names = "tx", "rx"; + assigned-clocks = <&gcc SDC2_CLK>; + assigned-clock-rates = <400000>; }; tcsr: syscon@1a400000 {