| Message ID | 20221001185321.492532-1-martin.botka@somainline.org (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [1/1] arm64: dts: qcom: sm6125: Add dispcc node | expand |
On 1.10.2022 20:53, Martin Botka wrote: > Add the dispcc node for the newly added DISPCC > driver for Qualcomm Technology Inc's SM6125 SoC. > > Signed-off-by: Martin Botka <martin.botka@somainline.org> > --- > arch/arm64/boot/dts/qcom/sm6125.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi > index 62f216bfca4f..ffbcee009279 100644 > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi > @@ -3,6 +3,7 @@ > * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> > */ > > +#include <dt-bindings/clock/qcom,dispcc-sm6125.h> > #include <dt-bindings/clock/qcom,gcc-sm6125.h> > #include <dt-bindings/clock/qcom,rpmcc.h> > #include <dt-bindings/gpio/gpio.h> > @@ -367,6 +368,17 @@ soc { > ranges = <0x00 0x00 0x00 0xffffffff>; > compatible = "simple-bus"; > > + dispcc: clock-controller@5f00000 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "qcom,dispcc-sm6125"; > + reg = <0x5f00000 0x20000>; Please pad the address to 8 hex digits and sort the properties properly. > + clocks = <&gcc GCC_DISP_AHB_CLK>; > + clock-names = "cfg_ahb_clk"; This driver does not expect this clock. It does however expect: bi_tcxo dp_phy_pll_link_clk dp_phy_pll_vco_div_clk dsi0_phy_pll_out_byteclk dsi0_phy_pll_out_dsiclk dsi1_phy_pll_out_dsiclk gcc_disp_gpll0_div_clk_src Konrad > + #clock-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > tcsr_mutex: hwlock@340000 { > compatible = "qcom,tcsr-mutex"; > reg = <0x00340000 0x20000>;
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 62f216bfca4f..ffbcee009279 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> */ +#include <dt-bindings/clock/qcom,dispcc-sm6125.h> #include <dt-bindings/clock/qcom,gcc-sm6125.h> #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/gpio/gpio.h> @@ -367,6 +368,17 @@ soc { ranges = <0x00 0x00 0x00 0xffffffff>; compatible = "simple-bus"; + dispcc: clock-controller@5f00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,dispcc-sm6125"; + reg = <0x5f00000 0x20000>; + clocks = <&gcc GCC_DISP_AHB_CLK>; + clock-names = "cfg_ahb_clk"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + tcsr_mutex: hwlock@340000 { compatible = "qcom,tcsr-mutex"; reg = <0x00340000 0x20000>;
Add the dispcc node for the newly added DISPCC driver for Qualcomm Technology Inc's SM6125 SoC. Signed-off-by: Martin Botka <martin.botka@somainline.org> --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)