| Message ID | 20221001190807.358691-3-marijn.suijten@somainline.org (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | drm: Fix math issues in MSM DSC implementation | expand |
On 1.10.2022 21:08, Marijn Suijten wrote: > slice_per_intf is already computed for intf_width, which holds the same > value as hdisplay. > > Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration") > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > drivers/gpu/drm/msm/dsi/dsi_host.c | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c > index e05bae647431..cb6f2fa11f58 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c > @@ -842,7 +842,7 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, > static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay) > { > struct drm_dsc_config *dsc = msm_host->dsc; > - u32 reg, intf_width, reg_ctrl, reg_ctrl2; > + u32 reg, reg_ctrl, reg_ctrl2; > u32 slice_per_intf, total_bytes_per_intf; > u32 pkt_per_line; > u32 bytes_in_slice; > @@ -851,8 +851,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod > /* first calculate dsc parameters and then program > * compress mode registers > */ > - intf_width = hdisplay; > - slice_per_intf = DIV_ROUND_UP(intf_width, dsc->slice_width); > + slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width); > > /* If slice_per_pkt is greater than slice_per_intf > * then default to 1. This can happen during partial > @@ -861,7 +860,6 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod > if (slice_per_intf > dsc->slice_count) > dsc->slice_count = 1; > > - slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width); > bytes_in_slice = DIV_ROUND_UP(dsc->slice_width * dsc->bits_per_pixel, 8); > > dsc->slice_chunk_size = bytes_in_slice;
On Sat, Oct 01, 2022 at 09:08:04PM +0200, Marijn Suijten wrote: > slice_per_intf is already computed for intf_width, which holds the same > value as hdisplay. > > Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration") > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> > --- > drivers/gpu/drm/msm/dsi/dsi_host.c | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c > index e05bae647431..cb6f2fa11f58 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c > @@ -842,7 +842,7 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, > static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay) > { > struct drm_dsc_config *dsc = msm_host->dsc; > - u32 reg, intf_width, reg_ctrl, reg_ctrl2; > + u32 reg, reg_ctrl, reg_ctrl2; > u32 slice_per_intf, total_bytes_per_intf; > u32 pkt_per_line; > u32 bytes_in_slice; > @@ -851,8 +851,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod > /* first calculate dsc parameters and then program > * compress mode registers > */ > - intf_width = hdisplay; > - slice_per_intf = DIV_ROUND_UP(intf_width, dsc->slice_width); > + slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width); > > /* If slice_per_pkt is greater than slice_per_intf > * then default to 1. This can happen during partial > @@ -861,7 +860,6 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod > if (slice_per_intf > dsc->slice_count) > dsc->slice_count = 1; > > - slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width); > bytes_in_slice = DIV_ROUND_UP(dsc->slice_width * dsc->bits_per_pixel, 8); > > dsc->slice_chunk_size = bytes_in_slice; > -- > 2.37.3 >
On 10/1/2022 12:08 PM, Marijn Suijten wrote: > slice_per_intf is already computed for intf_width, which holds the same > value as hdisplay. > > Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration") > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> LGTM, Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > --- > drivers/gpu/drm/msm/dsi/dsi_host.c | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c > index e05bae647431..cb6f2fa11f58 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c > @@ -842,7 +842,7 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, > static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay) > { > struct drm_dsc_config *dsc = msm_host->dsc; > - u32 reg, intf_width, reg_ctrl, reg_ctrl2; > + u32 reg, reg_ctrl, reg_ctrl2; > u32 slice_per_intf, total_bytes_per_intf; > u32 pkt_per_line; > u32 bytes_in_slice; > @@ -851,8 +851,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod > /* first calculate dsc parameters and then program > * compress mode registers > */ > - intf_width = hdisplay; > - slice_per_intf = DIV_ROUND_UP(intf_width, dsc->slice_width); > + slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width); > > /* If slice_per_pkt is greater than slice_per_intf > * then default to 1. This can happen during partial > @@ -861,7 +860,6 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod > if (slice_per_intf > dsc->slice_count) > dsc->slice_count = 1; > > - slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width); > bytes_in_slice = DIV_ROUND_UP(dsc->slice_width * dsc->bits_per_pixel, 8); > > dsc->slice_chunk_size = bytes_in_slice;
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index e05bae647431..cb6f2fa11f58 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -842,7 +842,7 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay) { struct drm_dsc_config *dsc = msm_host->dsc; - u32 reg, intf_width, reg_ctrl, reg_ctrl2; + u32 reg, reg_ctrl, reg_ctrl2; u32 slice_per_intf, total_bytes_per_intf; u32 pkt_per_line; u32 bytes_in_slice; @@ -851,8 +851,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod /* first calculate dsc parameters and then program * compress mode registers */ - intf_width = hdisplay; - slice_per_intf = DIV_ROUND_UP(intf_width, dsc->slice_width); + slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width); /* If slice_per_pkt is greater than slice_per_intf * then default to 1. This can happen during partial @@ -861,7 +860,6 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod if (slice_per_intf > dsc->slice_count) dsc->slice_count = 1; - slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width); bytes_in_slice = DIV_ROUND_UP(dsc->slice_width * dsc->bits_per_pixel, 8); dsc->slice_chunk_size = bytes_in_slice;
slice_per_intf is already computed for intf_width, which holds the same value as hdisplay. Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> --- drivers/gpu/drm/msm/dsi/dsi_host.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)