From patchwork Wed Oct 5 09:07:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 12999077 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 872F0C4332F for ; Wed, 5 Oct 2022 09:08:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230156AbiJEJIv (ORCPT ); Wed, 5 Oct 2022 05:08:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229477AbiJEJIW (ORCPT ); Wed, 5 Oct 2022 05:08:22 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E2967694B; Wed, 5 Oct 2022 02:08:07 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29597JO2016971; Wed, 5 Oct 2022 09:07:58 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=SP4Y9BgfE42D6Oc8eIt8Kgqn2zuvP2VZ7va2Ala/Aqg=; b=bZI72s+boI19QMikaGplQUkVYzT8Bty5YG4QMwKChemrbNHhTJ2Y+krV8jlu7RNIv+q4 ej51z2FPssQ4BZytSh4vhAzp45293uS8jeyVubqXbvjRoCFG2h6KbH37TCLzlk5DsYm9 Zox+Rqq/LBK1oPxnOP/6Q/0oi3FdNLEEKavAKZ0saIB7nPsxiPBqTUHn679M/2+xAaJE cB06aw2ll9jS1AAHvHSoDCWfHmiSV0389ISuyr8MPxogRia+WIaoLRYzMx0aTbjBWENh QQRF5pQYK+p17eBo1K8H266pc103ItQrvXGk0DQebzk2BCGPSEJRzTfvlQRecgefEG8J pA== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3k0esctw9v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 05 Oct 2022 09:07:57 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29597vYZ006155 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 5 Oct 2022 09:07:57 GMT Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 5 Oct 2022 02:07:51 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , Stephen Boyd , Dmitry Baryshkov , Philipp Zabel CC: Douglas Anderson , , Akhil P Oommen , Abhinav Kumar , Daniel Vetter , David Airlie , Krzysztof Kozlowski , Rob Herring , "Sean Paul" , , Subject: [PATCH v7 5/6] dt-bindings: drm/msm/gpu: Add optional resets Date: Wed, 5 Oct 2022 14:37:03 +0530 Message-ID: <20221005143618.v7.5.Ieffadd08a071a233213ced4406bf84bb5922ab9a@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1664960824-20951-1-git-send-email-quic_akhilpo@quicinc.com> References: <1664960824-20951-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 9lQHNYY-FBHr4AFisXlkzqXgCDDlSX7j X-Proofpoint-ORIG-GUID: 9lQHNYY-FBHr4AFisXlkzqXgCDDlSX7j X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-04_09,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 phishscore=0 bulkscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210050057 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add an optional reference to GPUCC reset which can be used to ensure cx gdsc collapse during gpu recovery. Signed-off-by: Akhil P Oommen Acked-by: Rob Herring Acked-by: Krzysztof Kozlowski --- (no changes since v5) Changes in v5: - Nit: Remove a duplicate blank line (Krzysztof) Changes in v4: - New patch in v4 Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 3397bc3..408ed97 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -109,6 +109,12 @@ properties: For GMU attached devices a phandle to the GMU device that will control the power for the GPU. + resets: + maxItems: 1 + + reset-names: + items: + - const: cx_collapse required: - compatible