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[v3,1/6] dt-bindings: soc: qcom: Update devicetree binding document for rpmh-rsc

Message ID 20221018152837.619426-2-ulf.hansson@linaro.org (mailing list archive)
State Accepted
Headers show
Series soc: qcom: Add APSS RSC to the CPU cluster PM domain | expand

Commit Message

Ulf Hansson Oct. 18, 2022, 3:28 p.m. UTC 
From: Maulik Shah <quic_mkshah@quicinc.com>

The change documents power-domains property for RSC device.
This optional property points to corresponding PM domain node.

Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450
---
 .../devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml          | 5 +++++
 1 file changed, 5 insertions(+)
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Patch

diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
index 4a50f1d27724..b246500d3d5d 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
@@ -99,6 +99,9 @@  properties:
       - const: drv-2
       - const: drv-3
 
+  power-domains:
+    maxItems: 1
+
   bcm-voter:
     $ref: /schemas/interconnect/qcom,bcm-voter.yaml#
 
@@ -151,6 +154,7 @@  examples:
                           <SLEEP_TCS   3>,
                           <WAKE_TCS    3>,
                           <CONTROL_TCS 1>;
+        power-domains = <&CLUSTER_PD>;
       };
 
   - |
@@ -197,6 +201,7 @@  examples:
                           <SLEEP_TCS   3>,
                           <WAKE_TCS    3>,
                           <CONTROL_TCS 0>;
+        power-domains = <&CLUSTER_PD>;
 
         clock-controller {
             compatible = "qcom,sm8350-rpmh-clk";