| Message ID | 20221111145919.221159-4-angelogioacchino.delregno@collabora.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support for Qualcomm's legacy IOMMU v2 | expand |
On 11/11/2022 2:59 pm, AngeloGioacchino Del Regno wrote: > In preparation for adding a proper context bank reset sequence in > qcom_iommu, add a definition for the implementation defined Fault > Status Restore register (FSRRESTORE). It's not implementation defined, it's architectural. But I don't follow why we should need this. If we're resetting FSR, we don't need to restore any previous value to it; all we want to do is clear it, which we do already via its own mechanism. Thanks, Robin. > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h > index 703fd5817ec1..5015138799c5 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h > @@ -219,6 +219,7 @@ enum arm_smmu_cbar_type { > ARM_SMMU_FSR_TF | \ > ARM_SMMU_FSR_IGN) > > +#define ARM_SMMU_CB_FSRRESTORE 0x5c > #define ARM_SMMU_CB_FAR 0x60 > > #define ARM_SMMU_CB_FSYNR0 0x68
Il 11/11/22 16:18, Robin Murphy ha scritto: > On 11/11/2022 2:59 pm, AngeloGioacchino Del Regno wrote: >> In preparation for adding a proper context bank reset sequence in >> qcom_iommu, add a definition for the implementation defined Fault >> Status Restore register (FSRRESTORE). > > It's not implementation defined, it's architectural. But I don't follow why we > should need this. If we're resetting FSR, we don't need to restore any previous > value to it; all we want to do is clear it, which we do already via its own mechanism. > The spec says "configurations" -> implementation defined whether the system implements stage 1 translation.... and that's how I got confused about it, sorry. Thanks for the review, this clears up my doubts: I can reset FSR without caring about FSRRESTORE. I'll send a v3 ASAP. Regards, Angelo > Thanks, > Robin. > >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> >> --- >> drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h >> b/drivers/iommu/arm/arm-smmu/arm-smmu.h >> index 703fd5817ec1..5015138799c5 100644 >> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h >> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h >> @@ -219,6 +219,7 @@ enum arm_smmu_cbar_type { >> ARM_SMMU_FSR_TF | \ >> ARM_SMMU_FSR_IGN) >> +#define ARM_SMMU_CB_FSRRESTORE 0x5c >> #define ARM_SMMU_CB_FAR 0x60 >> #define ARM_SMMU_CB_FSYNR0 0x68
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 703fd5817ec1..5015138799c5 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -219,6 +219,7 @@ enum arm_smmu_cbar_type { ARM_SMMU_FSR_TF | \ ARM_SMMU_FSR_IGN) +#define ARM_SMMU_CB_FSRRESTORE 0x5c #define ARM_SMMU_CB_FAR 0x60 #define ARM_SMMU_CB_FSYNR0 0x68
In preparation for adding a proper context bank reset sequence in qcom_iommu, add a definition for the implementation defined Fault Status Restore register (FSRRESTORE). Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + 1 file changed, 1 insertion(+)