From patchwork Tue Nov 15 13:30:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 13043691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5268C43219 for ; Tue, 15 Nov 2022 13:31:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229490AbiKONbP (ORCPT ); Tue, 15 Nov 2022 08:31:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229700AbiKONbP (ORCPT ); Tue, 15 Nov 2022 08:31:15 -0500 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC93DE58 for ; Tue, 15 Nov 2022 05:31:13 -0800 (PST) Received: by mail-ed1-x536.google.com with SMTP id 21so21899195edv.3 for ; Tue, 15 Nov 2022 05:31:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=BI4uKN83KwpFv+aZH8WcfU1uC+N8zfagUkvOFMX2f/0=; b=paG/2fJENIvm8NnWAawUhhBzGSPdHRUpmbX4bOrjkAokwgW0r0gNTXCK9Zf+jwsSax k8F1TG1paJuubjAzS5iLwmaEavsKZkxKPlXnDnjEok59ScH5ZjSdN+xtgF6dasadbWXl R/nbD24qHP7qcJ/VBNcX68QJhF60mKMl8CBp1Oxc6oMngar7Uh6Ec427ORMXsM93P1xQ VlTuH6S5YVIScNueY0JEMKkQ1JinpLtVv712a7i/XwL26wZ+aaK+POyI8QMHqxzUkd1F ftru4A7QfO8njAqTbaYU1NgA4Nkvbi6IKQXydF95oYdU225WFkcxZqO0bF4FaLef0XNA JMlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BI4uKN83KwpFv+aZH8WcfU1uC+N8zfagUkvOFMX2f/0=; b=SMueag0zxdeGxhZtYqU4qBVIHwAQwLAsocJ3ASPZHsMoC8V0u5fNUPdmilJ24M0ilD Xdo7YQBJ0MQFFpx3/2ptTgnJ5JUQe6aXVB+6dHSwEt+gdna0b9rchfjdYYRZ8nGw9k/d BWxSWzLfo+tA57VJAlaDn8l/o1CFB+HL4ORY8vu02J2PW2sLuvsmAH5siwTKvO9FcpvF jnt8zSyIaAeQxVpKXCApHra0BOWFOQKshYmUu71aqp9tself1FhTFuSOqDsErd1y8fnH 8kp8f5q5zqCHThLnCm3UrfUH6L7JKMi1JP3XD8X5ZR9gXQgpKsrfalbBYtVSwbkLgwwr eH5g== X-Gm-Message-State: ANoB5plvtmlOAa3yH+Na6dpw6kL6jVdOIYaDtWs8Z+NJikl5h2sk94y1 K2QP6AmOmJ4Vc6kOBAyENdRk0A== X-Google-Smtp-Source: AA0mqf7JZToraL1ximlhe1IQa5XejnrUhUva884fFu71/bfihz2zI7eZX+2nHb5XQCXMz8jq9lSo7A== X-Received: by 2002:aa7:d64a:0:b0:45b:cb6b:c342 with SMTP id v10-20020aa7d64a000000b0045bcb6bc342mr15099503edr.282.1668519072342; Tue, 15 Nov 2022 05:31:12 -0800 (PST) Received: from prec5560.. (freifunk-gw.bsa1-cpe1.syseleven.net. [176.74.57.43]) by smtp.gmail.com with ESMTPSA id q22-20020aa7d456000000b004618f2127d2sm6162176edr.57.2022.11.15.05.31.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Nov 2022 05:31:11 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, quic_kalyant@quicinc.com, swboyd@chromium.org, robert.foss@linaro.org, angelogioacchino.delregno@somainline.org, loic.poulain@linaro.org, quic_khsieh@quicinc.com, quic_vpolimer@quicinc.com, vkoul@kernel.org, dianders@chromium.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org, quic_jesszhan@quicinc.com, andersson@kernel.org Subject: [PATCH v2 01/12] dt-bindings: display: msm: Add qcom,sm8350-dpu binding Date: Tue, 15 Nov 2022 14:30:54 +0100 Message-Id: <20221115133105.980877-2-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221115133105.980877-1-robert.foss@linaro.org> References: <20221115133105.980877-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Mobile Display Subsystem (MDSS) encapsulates sub-blocks like DPU display controller, DSI etc. Add YAML schema for DPU device tree bindings Signed-off-by: Robert Foss Reviewed-by: Rob Herring --- .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 ++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml new file mode 100644 index 000000000000..120500395c9a --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 Display DPU + +maintainers: + - Robert Foss + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8350-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display ahb clock + - description: Display lut clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-controller@ae01000 { + compatible = "qcom,sm8350-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; +...