| Message ID | 20221213-sm6350-cci-v1-3-e5d0c36e0c4f@fairphone.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add CCI bus support for SM6350 | expand |
On 20.01.2023 12:11, Luca Weiss wrote: > Add nodes for the two CCI blocks found on SM6350. > > The first contains two i2c busses and while the second one might also > contains two busses, the downstream kernel only has one configured, and > some boards use the GPIOs for the potential cci1_i2c1 one other > purposes, so leave that one unconfigured. > > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> > --- > arch/arm64/boot/dts/qcom/sm6350.dtsi | 132 +++++++++++++++++++++++++++++++++++ > 1 file changed, 132 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi > index 300ced5cda57..666c1c80e4e6 100644 > --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi > @@ -6,6 +6,7 @@ > > #include <dt-bindings/clock/qcom,gcc-sm6350.h> > #include <dt-bindings/clock/qcom,rpmh.h> > +#include <dt-bindings/clock/qcom,sm6350-camcc.h> > #include <dt-bindings/dma/qcom-gpi.h> > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/interconnect/qcom,icc.h> > @@ -1435,6 +1436,95 @@ usb_1_dwc3: usb@a600000 { > }; > }; > > + cci0: cci@ac4a000 { > + compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; > + #address-cells = <1>; > + #size-cells = <0>; These two belong at the bottom > + > + reg = <0 0x0ac4a000 0 0x1000>; > + interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; > + power-domains = <&camcc TITAN_TOP_GDSC>; > + > + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, > + <&camcc CAMCC_SOC_AHB_CLK>, > + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, > + <&camcc CAMCC_CPAS_AHB_CLK>, > + <&camcc CAMCC_CCI_0_CLK>, > + <&camcc CAMCC_CCI_0_CLK_SRC>; > + clock-names = "camnoc_axi", > + "soc_ahb", > + "slow_ahb_src", > + "cpas_ahb", > + "cci", > + "cci_src"; > + > + assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, > + <&camcc CAMCC_CCI_0_CLK>; > + assigned-clock-rates = <80000000>, <37500000>; > + > + pinctrl-names = "default", "sleep"; Please move pinctrl-names below pinctrl-N for consistency with other properties ending with -names. > + pinctrl-0 = <&cci0_default &cci1_default>; > + pinctrl-1 = <&cci0_sleep &cci1_sleep>; > + > + status = "disabled"; > + > + cci0_i2c0: i2c-bus@0 { > + reg = <0>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + cci0_i2c1: i2c-bus@1 { > + reg = <1>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > + cci1: cci@ac4b000 { > + compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + reg = <0 0x0ac4b000 0 0x1000>; > + interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; > + power-domains = <&camcc TITAN_TOP_GDSC>; > + > + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, > + <&camcc CAMCC_SOC_AHB_CLK>, > + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, > + <&camcc CAMCC_CPAS_AHB_CLK>, > + <&camcc CAMCC_CCI_1_CLK>, > + <&camcc CAMCC_CCI_1_CLK_SRC>; > + clock-names = "camnoc_axi", > + "soc_ahb", > + "slow_ahb_src", > + "cpas_ahb", > + "cci", > + "cci_src"; > + > + assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, > + <&camcc CAMCC_CCI_1_CLK>; > + assigned-clock-rates = <80000000>, <37500000>; > + > + pinctrl-names = "default", "sleep"; > + pinctrl-0 = <&cci2_default>; > + pinctrl-1 = <&cci2_sleep>; > + > + status = "disabled"; > + > + cci1_i2c0: i2c-bus@0 { > + reg = <0>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */ > + }; > + > camcc: clock-controller@ad00000 { > compatible = "qcom,sm6350-camcc"; > reg = <0 0x0ad00000 0 0x16000>; > @@ -1522,6 +1612,48 @@ tlmm: pinctrl@f100000 { > #interrupt-cells = <2>; > gpio-ranges = <&tlmm 0 0 157>; > > + cci0_default: cci0-default-state { > + pins = "gpio39", "gpio40"; > + function = "cci_i2c"; > + bias-pull-up; Most other pin definitions in our directory have bias properties below drive-strength, please reorder. Konrad > + drive-strength = <2>; > + }; > + > + cci0_sleep: cci0-sleep-state { > + pins = "gpio39", "gpio40"; > + function = "cci_i2c"; > + bias-pull-down; > + drive-strength = <2>; > + }; > + > + cci1_default: cci1-default-state { > + pins = "gpio41", "gpio42"; > + function = "cci_i2c"; > + bias-pull-up; > + drive-strength = <2>; > + }; > + > + cci1_sleep: cci1-sleep-state { > + pins = "gpio41", "gpio42"; > + function = "cci_i2c"; > + bias-pull-down; > + drive-strength = <2>; > + }; > + > + cci2_default: cci2-default-state { > + pins = "gpio43", "gpio44"; > + function = "cci_i2c"; > + bias-pull-up; > + drive-strength = <2>; > + }; > + > + cci2_sleep: cci2-sleep-state { > + pins = "gpio43", "gpio44"; > + function = "cci_i2c"; > + bias-pull-down; > + drive-strength = <2>; > + }; > + > sdc2_off_state: sdc2-off-state { > clk-pins { > pins = "sdc2_clk"; >
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 300ced5cda57..666c1c80e4e6 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/clock/qcom,gcc-sm6350.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sm6350-camcc.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interconnect/qcom,icc.h> @@ -1435,6 +1436,95 @@ usb_1_dwc3: usb@a600000 { }; }; + cci0: cci@ac4a000 { + compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac4a000 0 0x1000>; + interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SOC_AHB_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_0_CLK>, + <&camcc CAMCC_CCI_0_CLK_SRC>; + clock-names = "camnoc_axi", + "soc_ahb", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CCI_0_CLK>; + assigned-clock-rates = <80000000>, <37500000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + + status = "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac4b000 { + compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac4b000 0 0x1000>; + interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SOC_AHB_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_1_CLK>, + <&camcc CAMCC_CCI_1_CLK_SRC>; + clock-names = "camnoc_axi", + "soc_ahb", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CCI_1_CLK>; + assigned-clock-rates = <80000000>, <37500000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci2_default>; + pinctrl-1 = <&cci2_sleep>; + + status = "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */ + }; + camcc: clock-controller@ad00000 { compatible = "qcom,sm6350-camcc"; reg = <0 0x0ad00000 0 0x16000>; @@ -1522,6 +1612,48 @@ tlmm: pinctrl@f100000 { #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 157>; + cci0_default: cci0-default-state { + pins = "gpio39", "gpio40"; + function = "cci_i2c"; + bias-pull-up; + drive-strength = <2>; + }; + + cci0_sleep: cci0-sleep-state { + pins = "gpio39", "gpio40"; + function = "cci_i2c"; + bias-pull-down; + drive-strength = <2>; + }; + + cci1_default: cci1-default-state { + pins = "gpio41", "gpio42"; + function = "cci_i2c"; + bias-pull-up; + drive-strength = <2>; + }; + + cci1_sleep: cci1-sleep-state { + pins = "gpio41", "gpio42"; + function = "cci_i2c"; + bias-pull-down; + drive-strength = <2>; + }; + + cci2_default: cci2-default-state { + pins = "gpio43", "gpio44"; + function = "cci_i2c"; + bias-pull-up; + drive-strength = <2>; + }; + + cci2_sleep: cci2-sleep-state { + pins = "gpio43", "gpio44"; + function = "cci_i2c"; + bias-pull-down; + drive-strength = <2>; + }; + sdc2_off_state: sdc2-off-state { clk-pins { pins = "sdc2_clk";
Add nodes for the two CCI blocks found on SM6350. The first contains two i2c busses and while the second one might also contains two busses, the downstream kernel only has one configured, and some boards use the GPIOs for the potential cci1_i2c1 one other purposes, so leave that one unconfigured. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 132 +++++++++++++++++++++++++++++++++++ 1 file changed, 132 insertions(+)