| Message ID | 20230214162325.312057-6-robert.marko@sartura.hr (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | fca392586c99dc0acb5a15709c2560dd4b24f6a1 |
| Headers | show |
| Series | [1/7] dt-bindings: clock: split qcom,gcc-ipq4019 to separate file | expand |
On 14.02.2023 17:23, Robert Marko wrote: > Move pcnoc clocks up just after PLL-s to be able to use their > HW fields. > > Signed-off-by: Robert Marko <robert.marko@sartura.hr> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > drivers/clk/qcom/gcc-ipq4019.c | 74 +++++++++++++++++----------------- > 1 file changed, 37 insertions(+), 37 deletions(-) > > diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c > index f4bc587131c20..f2728dc1e5521 100644 > --- a/drivers/clk/qcom/gcc-ipq4019.c > +++ b/drivers/clk/qcom/gcc-ipq4019.c > @@ -499,6 +499,43 @@ static struct clk_fepll gcc_fepllwcss5g_clk = { > .pll_vco = &gcc_fepll_vco, > }; > > +static const struct freq_tbl ftbl_gcc_pcnoc_ahb_clk[] = { > + F(48000000, P_XO, 1, 0, 0), > + F(100000000, P_FEPLL200, 2, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 gcc_pcnoc_ahb_clk_src = { > + .cmd_rcgr = 0x21024, > + .hid_width = 5, > + .parent_map = gcc_xo_200_500_map, > + .freq_tbl = ftbl_gcc_pcnoc_ahb_clk, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "gcc_pcnoc_ahb_clk_src", > + .parent_names = gcc_xo_200_500, > + .num_parents = 3, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_branch pcnoc_clk_src = { > + .halt_reg = 0x21030, > + .clkr = { > + .enable_reg = 0x21030, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "pcnoc_clk_src", > + .parent_names = (const char *[]){ > + "gcc_pcnoc_ahb_clk_src", > + }, > + .num_parents = 1, > + .ops = &clk_branch2_ops, > + .flags = CLK_SET_RATE_PARENT | > + CLK_IS_CRITICAL, > + }, > + }, > +}; > + > static const struct freq_tbl ftbl_gcc_audio_pwm_clk[] = { > F(48000000, P_XO, 1, 0, 0), > F(200000000, P_FEPLL200, 1, 0, 0), > @@ -1541,43 +1578,6 @@ static struct clk_branch gcc_wcss5g_rtc_clk = { > }, > }; > > -static const struct freq_tbl ftbl_gcc_pcnoc_ahb_clk[] = { > - F(48000000, P_XO, 1, 0, 0), > - F(100000000, P_FEPLL200, 2, 0, 0), > - { } > -}; > - > -static struct clk_rcg2 gcc_pcnoc_ahb_clk_src = { > - .cmd_rcgr = 0x21024, > - .hid_width = 5, > - .parent_map = gcc_xo_200_500_map, > - .freq_tbl = ftbl_gcc_pcnoc_ahb_clk, > - .clkr.hw.init = &(struct clk_init_data){ > - .name = "gcc_pcnoc_ahb_clk_src", > - .parent_names = gcc_xo_200_500, > - .num_parents = 3, > - .ops = &clk_rcg2_ops, > - }, > -}; > - > -static struct clk_branch pcnoc_clk_src = { > - .halt_reg = 0x21030, > - .clkr = { > - .enable_reg = 0x21030, > - .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data){ > - .name = "pcnoc_clk_src", > - .parent_names = (const char *[]){ > - "gcc_pcnoc_ahb_clk_src", > - }, > - .num_parents = 1, > - .ops = &clk_branch2_ops, > - .flags = CLK_SET_RATE_PARENT | > - CLK_IS_CRITICAL, > - }, > - }, > -}; > - > static struct clk_regmap *gcc_ipq4019_clocks[] = { > [AUDIO_CLK_SRC] = &audio_clk_src.clkr, > [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c index f4bc587131c20..f2728dc1e5521 100644 --- a/drivers/clk/qcom/gcc-ipq4019.c +++ b/drivers/clk/qcom/gcc-ipq4019.c @@ -499,6 +499,43 @@ static struct clk_fepll gcc_fepllwcss5g_clk = { .pll_vco = &gcc_fepll_vco, }; +static const struct freq_tbl ftbl_gcc_pcnoc_ahb_clk[] = { + F(48000000, P_XO, 1, 0, 0), + F(100000000, P_FEPLL200, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcnoc_ahb_clk_src = { + .cmd_rcgr = 0x21024, + .hid_width = 5, + .parent_map = gcc_xo_200_500_map, + .freq_tbl = ftbl_gcc_pcnoc_ahb_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_pcnoc_ahb_clk_src", + .parent_names = gcc_xo_200_500, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch pcnoc_clk_src = { + .halt_reg = 0x21030, + .clkr = { + .enable_reg = 0x21030, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "pcnoc_clk_src", + .parent_names = (const char *[]){ + "gcc_pcnoc_ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = CLK_SET_RATE_PARENT | + CLK_IS_CRITICAL, + }, + }, +}; + static const struct freq_tbl ftbl_gcc_audio_pwm_clk[] = { F(48000000, P_XO, 1, 0, 0), F(200000000, P_FEPLL200, 1, 0, 0), @@ -1541,43 +1578,6 @@ static struct clk_branch gcc_wcss5g_rtc_clk = { }, }; -static const struct freq_tbl ftbl_gcc_pcnoc_ahb_clk[] = { - F(48000000, P_XO, 1, 0, 0), - F(100000000, P_FEPLL200, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_pcnoc_ahb_clk_src = { - .cmd_rcgr = 0x21024, - .hid_width = 5, - .parent_map = gcc_xo_200_500_map, - .freq_tbl = ftbl_gcc_pcnoc_ahb_clk, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pcnoc_ahb_clk_src", - .parent_names = gcc_xo_200_500, - .num_parents = 3, - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_branch pcnoc_clk_src = { - .halt_reg = 0x21030, - .clkr = { - .enable_reg = 0x21030, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "pcnoc_clk_src", - .parent_names = (const char *[]){ - "gcc_pcnoc_ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - .flags = CLK_SET_RATE_PARENT | - CLK_IS_CRITICAL, - }, - }, -}; - static struct clk_regmap *gcc_ipq4019_clocks[] = { [AUDIO_CLK_SRC] = &audio_clk_src.clkr, [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
Move pcnoc clocks up just after PLL-s to be able to use their HW fields. Signed-off-by: Robert Marko <robert.marko@sartura.hr> --- drivers/clk/qcom/gcc-ipq4019.c | 74 +++++++++++++++++----------------- 1 file changed, 37 insertions(+), 37 deletions(-)