| Message ID | 20230216125257.112300-9-brgl@bgdev.pl (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs | expand |
On 16.02.2023 13:52, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > Enable the high-speed UART port connected to the GNSS controller on the > sa8775p-adp development board. > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > --- > arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 34 +++++++++++++++++++++++ > 1 file changed, 34 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > index d01ca3a9ee37..6f96907b335c 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > @@ -13,6 +13,7 @@ / { > > aliases { > serial0 = &uart10; > + serial1 = &uart12; > i2c18 = &i2c18; > spi16 = &spi16; > }; > @@ -66,6 +67,30 @@ qup_i2c18_default: qup-i2c18-state { > drive-strength = <2>; > bias-pull-up; > }; > + qup_uart12_default: [...] { qup_uart12_cts: [...] }; [...] pinctrl-0 = <&qup_uart12_default>; ? Konrad > + qup_uart12_cts: qup-uart12-cts-state { > + pins = "gpio52"; > + function = "qup1_se5"; > + bias-disable; > + }; > + > + qup_uart12_rts: qup-uart12-rts-state { > + pins = "gpio53"; > + function = "qup1_se5"; > + bias-pull-down; > + }; > + > + qup_uart12_tx: qup-uart12-tx-state { > + pins = "gpio54"; > + function = "qup1_se5"; > + bias-pull-up; > + }; > + > + qup_uart12_rx: qup-uart12-rx-state { > + pins = "gpio55"; > + function = "qup1_se5"; > + bias-pull-down; > + }; > }; > > &uart10 { > @@ -75,6 +100,15 @@ &uart10 { > status = "okay"; > }; > > +&uart12 { > + pinctrl-0 = <&qup_uart12_cts>, > + <&qup_uart12_rts>, > + <&qup_uart12_tx>, > + <&qup_uart12_rx>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > &xo_board_clk { > clock-frequency = <38400000>; > };
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index d01ca3a9ee37..6f96907b335c 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -13,6 +13,7 @@ / { aliases { serial0 = &uart10; + serial1 = &uart12; i2c18 = &i2c18; spi16 = &spi16; }; @@ -66,6 +67,30 @@ qup_i2c18_default: qup-i2c18-state { drive-strength = <2>; bias-pull-up; }; + + qup_uart12_cts: qup-uart12-cts-state { + pins = "gpio52"; + function = "qup1_se5"; + bias-disable; + }; + + qup_uart12_rts: qup-uart12-rts-state { + pins = "gpio53"; + function = "qup1_se5"; + bias-pull-down; + }; + + qup_uart12_tx: qup-uart12-tx-state { + pins = "gpio54"; + function = "qup1_se5"; + bias-pull-up; + }; + + qup_uart12_rx: qup-uart12-rx-state { + pins = "gpio55"; + function = "qup1_se5"; + bias-pull-down; + }; }; &uart10 { @@ -75,6 +100,15 @@ &uart10 { status = "okay"; }; +&uart12 { + pinctrl-0 = <&qup_uart12_cts>, + <&qup_uart12_rts>, + <&qup_uart12_tx>, + <&qup_uart12_rx>; + pinctrl-names = "default"; + status = "okay"; +}; + &xo_board_clk { clock-frequency = <38400000>; };