diff mbox series

[V2,2/2] arm64: dts: qcom: ipq5332: add support for the RDP468 variant

Message ID 20230323093120.20558-3-quic_kathirav@quicinc.com (mailing list archive)
State Accepted
Commit f1d33c902a1be727416fce3161db37a84d3f38d1
Headers show
Series Add initial support for RDP468 of IPQ5332 family | expand

Commit Message

Kathiravan Thirumoorthy March 23, 2023, 9:31 a.m. UTC 
Add the initial device tree support for the Reference Design
Platform(RDP) 468 based on IPQ5332 family of SoCs. This patch carries the
support for Console UART, SPI NOR, eMMC.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
Changes in V2:
	- Moved the 'reg' property after 'compatible'

 arch/arm64/boot/dts/qcom/Makefile           |   1 +
 arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts | 103 ++++++++++++++++++++
 2 files changed, 104 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts

Comments

Krzysztof Kozlowski March 23, 2023, 10:56 a.m. UTC | #1 
On 23/03/2023 10:31, Kathiravan T wrote:
> Add the initial device tree support for the Reference Design
> Platform(RDP) 468 based on IPQ5332 family of SoCs. This patch carries the
> support for Console UART, SPI NOR, eMMC.
> 
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> ---
> Changes in V2:
> 	- Moved the 'reg' property after 'compatible'
> 
>  arch/arm64/boot/dts/qcom/Makefile           |   1 +
>  arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts | 103 ++++++++++++++++++++
>  2 files changed, 104 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts

Hi,

Your v1 was reported that it does not build. Does this patch build fine?

Best regards,
Krzysztof
Kathiravan Thirumoorthy March 23, 2023, 11:17 a.m. UTC | #2 
On 3/23/2023 4:26 PM, Krzysztof Kozlowski wrote:
> On 23/03/2023 10:31, Kathiravan T wrote:
>> Add the initial device tree support for the Reference Design
>> Platform(RDP) 468 based on IPQ5332 family of SoCs. This patch carries the
>> support for Console UART, SPI NOR, eMMC.
>>
>> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
>> ---
>> Changes in V2:
>> 	- Moved the 'reg' property after 'compatible'
>>
>>   arch/arm64/boot/dts/qcom/Makefile           |   1 +
>>   arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts | 103 ++++++++++++++++++++
>>   2 files changed, 104 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
> Hi,
>
> Your v1 was reported that it does not build. Does this patch build fine?
As mentioned in the cover letter,

This series depends on the below which adds support the SPI NOR

https://lore.kernel.org/linux-arm-msm/20230320104530.30411-1-quic_kathirav@quicinc.com/

Thanks,

Kathiravan T.
Kathiravan Thirumoorthy March 23, 2023, 12:42 p.m. UTC | #3 
On 3/23/2023 4:47 PM, Kathiravan T wrote:
>
> On 3/23/2023 4:26 PM, Krzysztof Kozlowski wrote:
>> On 23/03/2023 10:31, Kathiravan T wrote:
>>> Add the initial device tree support for the Reference Design
>>> Platform(RDP) 468 based on IPQ5332 family of SoCs. This patch 
>>> carries the
>>> support for Console UART, SPI NOR, eMMC.
>>>
>>> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
>>> ---
>>> Changes in V2:
>>>     - Moved the 'reg' property after 'compatible'
>>>
>>>   arch/arm64/boot/dts/qcom/Makefile           |   1 +
>>>   arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts | 103 
>>> ++++++++++++++++++++
>>>   2 files changed, 104 insertions(+)
>>>   create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
>> Hi,
>>
>> Your v1 was reported that it does not build. Does this patch build fine?
> As mentioned in the cover letter,
>
> This series depends on the below which adds support the SPI NOR
>
> https://lore.kernel.org/linux-arm-msm/20230320104530.30411-1-quic_kathirav@quicinc.com/ 
>


Given that, this series and the dependent series has only DTS changes, 
and also both series has V2, is it okay If I squash them into single 
series and send it?


Thanks, Kathiravan T.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 1a29403400b7..79cf8373997f 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -4,6 +4,7 @@  dtb-$(CONFIG_ARCH_QCOM)	+= apq8094-sony-xperia-kitakami-karin_windy.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= apq8096-db820c.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= apq8096-ifc6640.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= ipq5332-mi01.2.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= ipq5332-rdp468.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c1.dtb
diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
new file mode 100644
index 000000000000..3b6a5cb8bf07
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
@@ -0,0 +1,103 @@ 
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * IPQ5332 RDP468 board device tree source
+ *
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ipq5332.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. IPQ5332 MI01.6";
+	compatible = "qcom,ipq5332-ap-mi01.6", "qcom,ipq5332";
+
+	aliases {
+		serial0 = &blsp1_uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0";
+	};
+};
+
+&blsp1_uart0 {
+	pinctrl-0 = <&serial_0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&blsp1_spi0 {
+	pinctrl-0 = <&spi_0_data_clk_pins &spi_0_cs_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	flash@0 {
+		compatible = "micron,n25q128a11", "jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <50000000>;
+	};
+};
+
+&sdhc {
+	bus-width = <4>;
+	max-frequency = <192000000>;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	non-removable;
+	pinctrl-0 = <&sdc_default_state>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&sleep_clk {
+	clock-frequency = <32000>;
+};
+
+&xo_board {
+	clock-frequency = <24000000>;
+};
+
+/* PINCTRL */
+
+&tlmm {
+	sdc_default_state: sdc-default-state {
+		clk-pins {
+			pins = "gpio13";
+			function = "sdc_clk";
+			drive-strength = <8>;
+			bias-disable;
+		};
+
+		cmd-pins {
+			pins = "gpio12";
+			function = "sdc_cmd";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		data-pins {
+			pins = "gpio8", "gpio9", "gpio10", "gpio11";
+			function = "sdc_data";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	spi_0_data_clk_pins: spi-0-data-clk-state {
+		pins = "gpio14", "gpio15", "gpio16";
+		function = "blsp0_spi";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	spi_0_cs_pins: spi-0-cs-state {
+		pins = "gpio17";
+		function = "blsp0_spi";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+};