From patchwork Thu May 18 01:14:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 13246023 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69AEAC7EE22 for ; Thu, 18 May 2023 01:14:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229500AbjERBOz (ORCPT ); Wed, 17 May 2023 21:14:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229611AbjERBOu (ORCPT ); Wed, 17 May 2023 21:14:50 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8146B422D for ; Wed, 17 May 2023 18:14:49 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34I0vaiF015463; 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Thu, 18 May 2023 01:14:39 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 17 May 2023 18:14:39 -0700 From: Jessica Zhang Date: Wed, 17 May 2023 18:14:29 -0700 Subject: [PATCH v13 3/9] drm/display/dsc: Add drm_dsc_get_bpp_int helper MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v13-3-d7581e7becec@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v13-0-d7581e7becec@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v13-0-d7581e7becec@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Kuogee Hsieh , "Daniel Vetter" , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , , , Jessica Zhang X-Mailer: b4 0.13-dev-bfdf5 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684372478; l=1320; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=sjbju8Rx6XS+h75pST5l3yWBEWY/UZ6jB96HfzV32oE=; b=RFV1l3H4Z4NRgxzmozJA6q3Pe3QR3jfK0TKbaQ3SFqAahhM8paZbSweGsN6i50wv5V1gUUE5r OyIsd4nbGOJBk7/zQ4MS6JcGa/C6uDA1PJAGLCnIzGHJSwUeB9vnSoG X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Mf2yVZuRkiy7KMPJLW7OhW7hUpXw3ldd X-Proofpoint-ORIG-GUID: Mf2yVZuRkiy7KMPJLW7OhW7hUpXw3ldd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-17_05,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 mlxlogscore=922 spamscore=0 mlxscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 adultscore=0 priorityscore=1501 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305180006 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add helper to get the integer value of drm_dsc_config.bits_per_pixel Reviewed-by: Marijn Suijten Reviewed-by: Dmitry Baryshkov Signed-off-by: Jessica Zhang --- include/drm/display/drm_dsc_helper.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h index e0cbc38ada26..7bf7e8ff8eb4 100644 --- a/include/drm/display/drm_dsc_helper.h +++ b/include/drm/display/drm_dsc_helper.h @@ -9,6 +9,7 @@ #define DRM_DSC_HELPER_H_ #include +#include enum drm_dsc_params_type { DRM_DSC_1_2_444, @@ -26,6 +27,12 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg); int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_type type); int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); +static inline u32 drm_dsc_get_bpp_int(const struct drm_dsc_config *dsc) +{ + WARN_ON_ONCE(dsc->bits_per_pixel & 0xf); + return dsc->bits_per_pixel >> 4; +} + static inline u8 drm_dsc_initial_scale_value(const struct drm_dsc_config *dsc) { return 8 * dsc->rc_model_size / (dsc->rc_model_size - dsc->initial_offset);