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[213.36.7.13]) by smtp.gmail.com with ESMTPSA id m22-20020a7bcb96000000b003f17131952fsm2388519wmi.29.2023.04.19.07.41.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 07:41:58 -0700 (PDT) From: Arnaud Vrac Date: Wed, 19 Apr 2023 16:41:12 +0200 Subject: [PATCH 05/11] drm/msm/dpu: allow using all lm mixer stages MIME-Version: 1.0 Message-Id: <20230419-dpu-tweaks-v1-5-d1bac46db075@freebox.fr> References: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> In-Reply-To: <20230419-dpu-tweaks-v1-0-d1bac46db075@freebox.fr> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Arnaud Vrac X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1211; i=avrac@freebox.fr; h=from:subject:message-id; bh=CDBIvOWtwi9aZ7RRIDQqd7SRtuQgF7hezIg0kgVuXhA=; b=owEBbQKS/ZANAwAIAXED/9m7NDSrAcsmYgBkP/2dJRmjvyQIHMA35EzFtdfeQCWdKsmoqxMyC KhTYcFPJ+OJAjMEAAEIAB0WIQSUwb/ndwkXHdZ/QQZxA//ZuzQ0qwUCZD/9nQAKCRBxA//ZuzQ0 q0X5D/0aSHCjp0ig81KYbJRs3J6FjRqaFku3XF7PaHPJLMriUUmk19hVcxaYBNWKsKxBq3f3k1+ SJL2G79OCXfM30ongZgZ57t4BMp/lmOrnOguLlj+6n5RLVJ8KvkGHMVL7pA5o/1YEMP6k1SVH5B sFhAc/t99qssE0rjEtIZDSR96Bg2ZRUaWBjBK8ddEnghwXtojkv0Udb7cJywJ25X7T3IH8RpXln +fA6sGohtUZ+T/a6ieO6p4Kk3bFUVG2p8MVzCFlMjkjdoWqdNTj5rc6IwNL8UR9R7PZED4bID7G ZzsZUtTbj/h13CL7UmnG28jvU2jUsHX5VLJOmrh0RgfKG4Gq2CX0FgEF9ejE1ISmJTxwf4npwK5 nMYyAVPdje7ca2sAx56wDAfKglSSahk9L7r8NAOb0ArKKe2qN4ZJ/DzmE1tfmFRon+xPuxwYLpj c61NMrfMeOM8ykBLgOSOwzUvUhzcrAhBlMDq4C73aZA8QTKD2BRwaqyBVa4IJY2A1MfClyuWInq QoVbFCxb71ZE3VHuv3GIyLfNuAWr2JOMj0KLYsragK1vDks+eOOWgdrzPA9FXFEeF7i+g2kZjYl L5ZkcSgBt10Jacwq8m6jQSUuwI0Wh6mX+UNFVRQoLxnf/Nf4aJRkFCo6bPMSCbs+GirNvCuC2ou 7vnXujDg35QAmKQ== X-Developer-Key: i=avrac@freebox.fr; a=openpgp; fpr=6225092072BB58E3CEEC091E75392A176D952DB4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The max_mixer_blendstages hw catalog property represents the number of planes that can be blended by the lm mixer, excluding the base stage, so adjust the check for the number of currently assigned planes accordingly. Signed-off-by: Arnaud Vrac Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 148921ed62f85..128ecdc145260 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -882,9 +882,9 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, r_pipe->sspp = NULL; pstate->stage = DPU_STAGE_BASE + pstate->base.normalized_zpos; - if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { - DPU_ERROR("> %d plane stages assigned\n", - pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); + if (pstate->stage > DPU_STAGE_BASE + pdpu->catalog->caps->max_mixer_blendstages) { + DPU_ERROR("> %d plane mixer stages assigned\n", + pdpu->catalog->caps->max_mixer_blendstages); return -EINVAL; }