| Message ID | 20230512122134.24339-7-quic_kbajaj@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | soc: qcom: llcc: Add support for QDU1000/QRU1000 | expand |
Hi Komal,
kernel test robot noticed the following build errors:
[auto build test ERROR on linus/master]
[also build test ERROR on v6.4-rc1 next-20230512]
[cannot apply to robh/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Komal-Bajaj/nvmem-qfprom-Add-support-for-secure-reading/20230512-202430
base: linus/master
patch link: https://lore.kernel.org/r/20230512122134.24339-7-quic_kbajaj%40quicinc.com
patch subject: [PATCH v3 06/10] soc: qcom: Add LLCC support for multi channel DDR
config: riscv-randconfig-r042-20230509 (https://download.01.org/0day-ci/archive/20230513/202305130303.wwdZb5hy-lkp@intel.com/config)
compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project b0fb98227c90adf2536c9ad644a74d5e92961111)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/52808ee1c4720767ab330b371d356ffbd8fe7235
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Komal-Bajaj/nvmem-qfprom-Add-support-for-secure-reading/20230512-202430
git checkout 52808ee1c4720767ab330b371d356ffbd8fe7235
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash drivers/soc/qcom/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202305130303.wwdZb5hy-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/soc/qcom/llcc-qcom.c:951:8: error: call to undeclared function 'nvmem_cell_read_u8'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
ret = nvmem_cell_read_u8(&pdev->dev, "multi_chan_ddr", cfg_index);
^
1 error generated.
vim +/nvmem_cell_read_u8 +951 drivers/soc/qcom/llcc-qcom.c
946
947 static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u8 *cfg_index)
948 {
949 int ret = 0;
950
> 951 ret = nvmem_cell_read_u8(&pdev->dev, "multi_chan_ddr", cfg_index);
952 if (ret == -ENOENT) {
953 *cfg_index = 0;
954 return 0;
955 }
956
957 return ret;
958 }
959
Hi Komal,
kernel test robot noticed the following build errors:
[auto build test ERROR on linus/master]
[also build test ERROR on v6.4-rc1 next-20230512]
[cannot apply to robh/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Komal-Bajaj/nvmem-qfprom-Add-support-for-secure-reading/20230512-202430
base: linus/master
patch link: https://lore.kernel.org/r/20230512122134.24339-7-quic_kbajaj%40quicinc.com
patch subject: [PATCH v3 06/10] soc: qcom: Add LLCC support for multi channel DDR
config: nios2-buildonly-randconfig-r001-20230509 (https://download.01.org/0day-ci/archive/20230513/202305130308.9zOC4OZC-lkp@intel.com/config)
compiler: nios2-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/52808ee1c4720767ab330b371d356ffbd8fe7235
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Komal-Bajaj/nvmem-qfprom-Add-support-for-secure-reading/20230512-202430
git checkout 52808ee1c4720767ab330b371d356ffbd8fe7235
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=nios2 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=nios2 SHELL=/bin/bash drivers/soc/qcom/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202305130308.9zOC4OZC-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/soc/qcom/llcc-qcom.c: In function 'qcom_llcc_get_cfg_index':
>> drivers/soc/qcom/llcc-qcom.c:951:15: error: implicit declaration of function 'nvmem_cell_read_u8'; did you mean 'nvmem_cell_read_u64'? [-Werror=implicit-function-declaration]
951 | ret = nvmem_cell_read_u8(&pdev->dev, "multi_chan_ddr", cfg_index);
| ^~~~~~~~~~~~~~~~~~
| nvmem_cell_read_u64
cc1: some warnings being treated as errors
vim +951 drivers/soc/qcom/llcc-qcom.c
946
947 static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u8 *cfg_index)
948 {
949 int ret = 0;
950
> 951 ret = nvmem_cell_read_u8(&pdev->dev, "multi_chan_ddr", cfg_index);
952 if (ret == -ENOENT) {
953 *cfg_index = 0;
954 return 0;
955 }
956
957 return ret;
958 }
959
On Fri, May 12, 2023 at 05:51:30PM +0530, Komal Bajaj wrote: > Add LLCC support for multi channel DDR configuration > based on a feature register. > > Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> > --- > drivers/soc/qcom/llcc-qcom.c | 32 +++++++++++++++++++++++++++++--- > 1 file changed, 29 insertions(+), 3 deletions(-) > > diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c > index 6cf373da5df9..1da337e7a378 100644 > --- a/drivers/soc/qcom/llcc-qcom.c > +++ b/drivers/soc/qcom/llcc-qcom.c > @@ -12,6 +12,7 @@ > #include <linux/kernel.h> > #include <linux/module.h> > #include <linux/mutex.h> > +#include <linux/nvmem-consumer.h> > #include <linux/of.h> > #include <linux/of_device.h> > #include <linux/regmap.h> > @@ -943,6 +944,19 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev, > return ret; > } > > +static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u8 *cfg_index) > +{ > + int ret = 0; First use is an assignment, no need to initialize here. > + > + ret = nvmem_cell_read_u8(&pdev->dev, "multi_chan_ddr", cfg_index); > + if (ret == -ENOENT) { > + *cfg_index = 0; Does nvmem_cell_read_u8() cahnge cfg_index when it fails with -ENOENT? > + return 0; > + } > + > + return ret; > +} > + > static int qcom_llcc_remove(struct platform_device *pdev) > { > /* Set the global pointer to a error code to avoid referencing it */ > @@ -975,11 +989,13 @@ static int qcom_llcc_probe(struct platform_device *pdev) > struct device *dev = &pdev->dev; > int ret, i; > struct platform_device *llcc_edac; > - const struct qcom_llcc_config *cfg; > + const struct qcom_llcc_config *cfg, *entry; > const struct llcc_slice_config *llcc_cfg; > u32 sz; > + u8 cfg_index; > u32 version; > struct regmap *regmap; > + u32 num_entries = 0; > > drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); > if (!drv_data) { > @@ -1040,8 +1056,18 @@ static int qcom_llcc_probe(struct platform_device *pdev) > > drv_data->version = version; > > - llcc_cfg = cfg[0]->sct_data; > - sz = cfg[0]->size; > + ret = qcom_llcc_get_cfg_index(pdev, &cfg_index); > + if (ret) > + goto err; > + > + for (entry = cfg; entry->sct_data; entry++, num_entries++); This is not readable, move the increment of num_entries out of there. > + if (cfg_index >= num_entries || cfg_index < 0) { How can cfg_index be negative? Regards, Bjorn > + ret = -EINVAL; > + goto err; > + } > + > + llcc_cfg = cfg[cfg_index].sct_data; > + sz = cfg[cfg_index].size; > > for (i = 0; i < sz; i++) > if (llcc_cfg[i].slice_id > drv_data->max_slices) > -- > 2.17.1 >
On 6/13/2023 10:41 PM, Bjorn Andersson wrote: > On Fri, May 12, 2023 at 05:51:30PM +0530, Komal Bajaj wrote: >> Add LLCC support for multi channel DDR configuration >> based on a feature register. >> >> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> >> --- >> drivers/soc/qcom/llcc-qcom.c | 32 +++++++++++++++++++++++++++++--- >> 1 file changed, 29 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c >> index 6cf373da5df9..1da337e7a378 100644 >> --- a/drivers/soc/qcom/llcc-qcom.c >> +++ b/drivers/soc/qcom/llcc-qcom.c >> @@ -12,6 +12,7 @@ >> #include <linux/kernel.h> >> #include <linux/module.h> >> #include <linux/mutex.h> >> +#include <linux/nvmem-consumer.h> >> #include <linux/of.h> >> #include <linux/of_device.h> >> #include <linux/regmap.h> >> @@ -943,6 +944,19 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev, >> return ret; >> } >> >> +static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u8 *cfg_index) >> +{ >> + int ret = 0; > First use is an assignment, no need to initialize here. Noted. > >> + >> + ret = nvmem_cell_read_u8(&pdev->dev, "multi_chan_ddr", cfg_index); >> + if (ret == -ENOENT) { >> + *cfg_index = 0; > Does nvmem_cell_read_u8() cahnge cfg_index when it fails with -ENOENT? No, if nvmem_cell_read_u8() fails with any error, cfg_index will not be changed. Thanks Komal >> + return 0; >> + } >> + >> + return ret; >> +} >> + >> static int qcom_llcc_remove(struct platform_device *pdev) >> { >> /* Set the global pointer to a error code to avoid referencing it */ >> @@ -975,11 +989,13 @@ static int qcom_llcc_probe(struct platform_device *pdev) >> struct device *dev = &pdev->dev; >> int ret, i; >> struct platform_device *llcc_edac; >> - const struct qcom_llcc_config *cfg; >> + const struct qcom_llcc_config *cfg, *entry; >> const struct llcc_slice_config *llcc_cfg; >> u32 sz; >> + u8 cfg_index; >> u32 version; >> struct regmap *regmap; >> + u32 num_entries = 0; >> >> drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); >> if (!drv_data) { >> @@ -1040,8 +1056,18 @@ static int qcom_llcc_probe(struct platform_device *pdev) >> >> drv_data->version = version; >> >> - llcc_cfg = cfg[0]->sct_data; >> - sz = cfg[0]->size; >> + ret = qcom_llcc_get_cfg_index(pdev, &cfg_index); >> + if (ret) >> + goto err; >> + >> + for (entry = cfg; entry->sct_data; entry++, num_entries++); > This is not readable, move the increment of num_entries out of there. > >> + if (cfg_index >= num_entries || cfg_index < 0) { > How can cfg_index be negative? > > Regards, > Bjorn > >> + ret = -EINVAL; >> + goto err; >> + } >> + >> + llcc_cfg = cfg[cfg_index].sct_data; >> + sz = cfg[cfg_index].size; >> >> for (i = 0; i < sz; i++) >> if (llcc_cfg[i].slice_id > drv_data->max_slices) >> -- >> 2.17.1 >>
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 6cf373da5df9..1da337e7a378 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -12,6 +12,7 @@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/mutex.h> +#include <linux/nvmem-consumer.h> #include <linux/of.h> #include <linux/of_device.h> #include <linux/regmap.h> @@ -943,6 +944,19 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev, return ret; } +static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u8 *cfg_index) +{ + int ret = 0; + + ret = nvmem_cell_read_u8(&pdev->dev, "multi_chan_ddr", cfg_index); + if (ret == -ENOENT) { + *cfg_index = 0; + return 0; + } + + return ret; +} + static int qcom_llcc_remove(struct platform_device *pdev) { /* Set the global pointer to a error code to avoid referencing it */ @@ -975,11 +989,13 @@ static int qcom_llcc_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; int ret, i; struct platform_device *llcc_edac; - const struct qcom_llcc_config *cfg; + const struct qcom_llcc_config *cfg, *entry; const struct llcc_slice_config *llcc_cfg; u32 sz; + u8 cfg_index; u32 version; struct regmap *regmap; + u32 num_entries = 0; drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) { @@ -1040,8 +1056,18 @@ static int qcom_llcc_probe(struct platform_device *pdev) drv_data->version = version; - llcc_cfg = cfg[0]->sct_data; - sz = cfg[0]->size; + ret = qcom_llcc_get_cfg_index(pdev, &cfg_index); + if (ret) + goto err; + + for (entry = cfg; entry->sct_data; entry++, num_entries++); + if (cfg_index >= num_entries || cfg_index < 0) { + ret = -EINVAL; + goto err; + } + + llcc_cfg = cfg[cfg_index].sct_data; + sz = cfg[cfg_index].size; for (i = 0; i < sz; i++) if (llcc_cfg[i].slice_id > drv_data->max_slices)
Add LLCC support for multi channel DDR configuration based on a feature register. Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> --- drivers/soc/qcom/llcc-qcom.c | 32 +++++++++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) -- 2.17.1