From patchwork Fri May 26 19:08:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 13257271 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35233C7EE23 for ; Fri, 26 May 2023 19:09:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243832AbjEZTJE (ORCPT ); Fri, 26 May 2023 15:09:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243464AbjEZTJD (ORCPT ); Fri, 26 May 2023 15:09:03 -0400 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 496DD135; Fri, 26 May 2023 12:09:00 -0700 (PDT) Received: by mail-ed1-x531.google.com with SMTP id 4fb4d7f45d1cf-51403554f1dso1647602a12.1; Fri, 26 May 2023 12:09:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1685128139; x=1687720139; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QMgZAckXx8VyIyvdPqZk+MsBx1jAUZv0/tmo2hWhZHU=; b=A6587J6isdh2rRAY5QiHXIiiLRAIstSnzsfxn31ZQQHfX98koKki73kOBk7smdJhRK lny+bzLxADkkSMIORh6NCXwlK47mkYte9X4b0gvHsL1HQHp0IrNRcBSg/6hLsKTPCUn9 /SsYa5/c+o0BsUoWVTPBWs1VF9ZXUIk/eKv2pJ2NfMEQ8KhRWNridsAE8QqoPU5bXIbQ QcPaiw6fS9Do0zopt16HdhEwvZtAtPHNIBYWwtaxqOOB4zSM4t4+hWt5Mza4VgX2ZLnm RJ7po8euzJgARrJpBFEMrvN0faEOXeJzJpviT/Rzb4fJmbaWvLlF0p2NybKTmfj+41yM fyZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685128139; x=1687720139; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QMgZAckXx8VyIyvdPqZk+MsBx1jAUZv0/tmo2hWhZHU=; b=kZ37RKnop7sc4sk/Uc/gVcjFxlyHc0m1uBNbN6KMz/XAF+gYVFKzl9EAVpFLjeyIIs fmRxM5lywrXm+gwEVNR+6M2zmLzSe3p4tyrTPfyLOkr5NAbFvJkCVYaneepIw26nF2x2 PsZRQQ2PTG2lost37uTbwW5oB1Ys8W7uPBGwFt3uSn6KnS1tk+IWIJBY0OgeNAxtt+V7 pCONzHmJ2M6FXLaJS9tr9v1tFkQJ1CN20gJF2hAMtK8Y6KTnaprh8IB6u0Ul1Q7QHfoW BD93b0iMuInEulWpVJRK1llGxz199FjJ9TU5dTk8GmPHna+mCIAYMrMe8pqxcQlWlP8P tIfg== X-Gm-Message-State: AC+VfDzE26PvfIcco/J4KlyST2kd/nT4dl9MZC7IS+WwSDcWAeNJ7eEC fzGDM0cet0fPcbFMkzAJztYFOPHV+DfNoA== X-Google-Smtp-Source: ACHHUZ5SlHvdAl9uxpdt50i3zUDS0Qm+ORnmkb9/7TjvC7VzOdPy017l9MVT0Ldnmiyj3NLbY/i+SQ== X-Received: by 2002:a17:906:7951:b0:966:54ac:17d7 with SMTP id l17-20020a170906795100b0096654ac17d7mr4115384ejo.76.1685128138557; Fri, 26 May 2023 12:08:58 -0700 (PDT) Received: from fedora.. (dh207-98-6.xnet.hr. [88.207.98.6]) by smtp.googlemail.com with ESMTPSA id q18-20020a170906b29200b0095844605bb8sm2507439ejz.10.2023.05.26.12.08.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 May 2023 12:08:58 -0700 (PDT) From: Robert Marko To: andersson@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH 2/2] clk: qcom: ipq6018: fix networking resets Date: Fri, 26 May 2023 21:08:55 +0200 Message-Id: <20230526190855.2941291-2-robimarko@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230526190855.2941291-1-robimarko@gmail.com> References: <20230526190855.2941291-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Networking resets in IPQ6018 all use bitmask as they require multiple bits to be set and cleared instead of a single bit. So, current networking resets have the same register and bit 0 set which is clearly incorrect. Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support") Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq6018.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c index abd97b939850f..b8310f29a8ff4 100644 --- a/drivers/clk/qcom/gcc-ipq6018.c +++ b/drivers/clk/qcom/gcc-ipq6018.c @@ -4520,24 +4520,24 @@ static const struct qcom_reset_map gcc_ipq6018_resets[] = { [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 }, [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 }, [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 }, - [GCC_PPE_FULL_RESET] = { 0x68014, 0 }, - [GCC_UNIPHY0_SOFT_RESET] = { 0x56004, 0 }, + [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = 0xf0000 }, + [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = 0x3ff2 }, [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 }, - [GCC_UNIPHY1_SOFT_RESET] = { 0x56104, 0 }, + [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = 0x32 }, [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 }, - [GCC_EDMA_HW_RESET] = { 0x68014, 0 }, - [GCC_NSSPORT1_RESET] = { 0x68014, 0 }, - [GCC_NSSPORT2_RESET] = { 0x68014, 0 }, - [GCC_NSSPORT3_RESET] = { 0x68014, 0 }, - [GCC_NSSPORT4_RESET] = { 0x68014, 0 }, - [GCC_NSSPORT5_RESET] = { 0x68014, 0 }, - [GCC_UNIPHY0_PORT1_ARES] = { 0x56004, 0 }, - [GCC_UNIPHY0_PORT2_ARES] = { 0x56004, 0 }, - [GCC_UNIPHY0_PORT3_ARES] = { 0x56004, 0 }, - [GCC_UNIPHY0_PORT4_ARES] = { 0x56004, 0 }, - [GCC_UNIPHY0_PORT5_ARES] = { 0x56004, 0 }, - [GCC_UNIPHY0_PORT_4_5_RESET] = { 0x56004, 0 }, - [GCC_UNIPHY0_PORT_4_RESET] = { 0x56004, 0 }, + [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = 0x300000 }, + [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = 0x1000003 }, + [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = 0x200000c }, + [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = 0x4000030 }, + [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = 0x8000300 }, + [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = 0x10000c00 }, + [GCC_UNIPHY0_PORT1_ARES] = { .reg = 0x56004, .bitmask = 0x30 }, + [GCC_UNIPHY0_PORT2_ARES] = { .reg = 0x56004, .bitmask = 0xc0 }, + [GCC_UNIPHY0_PORT3_ARES] = { .reg = 0x56004, .bitmask = 0x300 }, + [GCC_UNIPHY0_PORT4_ARES] = { .reg = 0x56004, .bitmask = 0xc00 }, + [GCC_UNIPHY0_PORT5_ARES] = { .reg = 0x56004, .bitmask = 0x3000 }, + [GCC_UNIPHY0_PORT_4_5_RESET] = { .reg = 0x56004, .bitmask = 0x3c02 }, + [GCC_UNIPHY0_PORT_4_RESET] = { .reg = 0x56004, .bitmask = 0xc02 }, [GCC_LPASS_BCR] = {0x1F000, 0}, [GCC_UBI32_TBU_BCR] = {0x65000, 0}, [GCC_LPASS_TBU_BCR] = {0x6C000, 0},