From patchwork Thu Jun 29 14:45:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrien Thierry X-Patchwork-Id: 13297077 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82613EB64DC for ; Thu, 29 Jun 2023 14:47:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231393AbjF2OrS (ORCPT ); Thu, 29 Jun 2023 10:47:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231784AbjF2OrQ (ORCPT ); Thu, 29 Jun 2023 10:47:16 -0400 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAA0B2D4A for ; Thu, 29 Jun 2023 07:46:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1688049985; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mJHAjr6KTZnVlwFWvOamTtWU7Nmn1qurp7u5WOjdc6M=; b=PVidxbV2P0oJrL6QGEnJEMndjeUsZ8w5R4HSqkOHFhWzTAtddorM/YnkLGyPq5LMDxUDsK ndKzOPA+0xIRx+rHvVoLaQ1KoAHo0lJdwHR6fQu16ootGOCosy360VRwO37SzIPgfc+QdS qUH0APdG3AD9nHFp+pjkOZJ3F+dIqIs= Received: from mail-qk1-f197.google.com (mail-qk1-f197.google.com [209.85.222.197]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-90-YxfGiou_OEewDfdVzJpZSQ-1; Thu, 29 Jun 2023 10:46:24 -0400 X-MC-Unique: YxfGiou_OEewDfdVzJpZSQ-1 Received: by mail-qk1-f197.google.com with SMTP id af79cd13be357-7659db633acso101005485a.0 for ; Thu, 29 Jun 2023 07:46:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688049983; x=1690641983; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mJHAjr6KTZnVlwFWvOamTtWU7Nmn1qurp7u5WOjdc6M=; b=IFr/HM/WXXQ460DG2Fd5wWcrMF9E9EWmvWgdW0mByNCvCoxQFNUwgEERPLHFbD9nlq 9rl4Bls946gps9wlZdG1azpzauq60FMzPHDuI3rjPjWjh7ZWd/MbMnlnpI+nlywO1FKf TAfd9U1JfbhyBLiw8hdwwu6QcRMaZZsFOdDD1XK1I1xGhDyKcvHdATdTR3q7ieOJJxDC hBHIVypYE9Z8s0CN3OqjsccjsGQGvckXVLaPVWg8OOOHW3aO+GAdJYjLJHIAtPz3/Z6t DW7E37NDIYqR+dKt6u1azIDzdH/+wXfU+8L5LG2BLYvoi5zxlr93WvfvtIJtAsdHCTrW TIWw== X-Gm-Message-State: AC+VfDxvIn3gzxdrS78SD3WbI7N5pGHeIyYmQIaL2RfS4/RrTSJSAWw7 0ruq6MGXuyPNEnrG/Cx/xCBDvAt/MvxG6kVx/EC50H6VNEOB3Q71RrhFpzg46DmeqkhZLetILk6 eejuScV5wU2/FLfFvwAKPCUus8Q== X-Received: by 2002:a05:6214:493:b0:62f:ffcc:337a with SMTP id pt19-20020a056214049300b0062fffcc337amr53542788qvb.25.1688049983502; Thu, 29 Jun 2023 07:46:23 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7ha+Mfs7Doj4shg6GNpLPTKkZCYV++sdbCYEyb8MOGt3lEwlYQ8NSoBGVyWNAjXMtZrjqRwQ== X-Received: by 2002:a05:6214:493:b0:62f:ffcc:337a with SMTP id pt19-20020a056214049300b0062fffcc337amr53542772qvb.25.1688049983271; Thu, 29 Jun 2023 07:46:23 -0700 (PDT) Received: from fedora.redhat.com ([107.171.218.122]) by smtp.gmail.com with ESMTPSA id a17-20020a0ccdd1000000b005dd8b9345b4sm7055590qvn.76.2023.06.29.07.46.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jun 2023 07:46:22 -0700 (PDT) From: Adrien Thierry To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Wesley Cheng , Manu Gautam , Stephen Boyd , Philipp Zabel Cc: Adrien Thierry , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v4 2/3] phy: qcom-snps-femto-v2: properly enable ref clock Date: Thu, 29 Jun 2023 10:45:39 -0400 Message-Id: <20230629144542.14906-3-athierry@redhat.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230629144542.14906-1-athierry@redhat.com> References: <20230629144542.14906-1-athierry@redhat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The driver is not enabling the ref clock, which thus gets disabled by the clk_disable_unused() initcall. This leads to the dwc3 controller failing to initialize if probed after clk_disable_unused() is called, for instance when the driver is built as a module. To fix this, switch to the clk_bulk API to handle both cfg_ahb and ref clocks at the proper places. Note that the cfg_ahb clock is currently not used by any device tree instantiation of the PHY. Work needs to be done separately to fix this. Link: https://lore.kernel.org/linux-arm-msm/ZEqvy+khHeTkC2hf@fedora/ Fixes: 51e8114f80d0 ("phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs") Signed-off-by: Adrien Thierry --- drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 63 ++++++++++++++----- 1 file changed, 48 insertions(+), 15 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c index 3335480fc395..6170f8fd118e 100644 --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c @@ -110,11 +110,13 @@ struct phy_override_seq { /** * struct qcom_snps_hsphy - snps hs phy attributes * + * @dev: device structure + * * @phy: generic phy * @base: iomapped memory space for snps hs phy * - * @cfg_ahb_clk: AHB2PHY interface clock - * @ref_clk: phy reference clock + * @num_clks: number of clocks + * @clks: array of clocks * @phy_reset: phy reset control * @vregs: regulator supplies bulk data * @phy_initialized: if PHY has been initialized correctly @@ -122,11 +124,13 @@ struct phy_override_seq { * @update_seq_cfg: tuning parameters for phy init */ struct qcom_snps_hsphy { + struct device *dev; + struct phy *phy; void __iomem *base; - struct clk *cfg_ahb_clk; - struct clk *ref_clk; + int num_clks; + struct clk_bulk_data *clks; struct reset_control *phy_reset; struct regulator_bulk_data vregs[SNPS_HS_NUM_VREGS]; @@ -135,6 +139,34 @@ struct qcom_snps_hsphy { struct phy_override_seq update_seq_cfg[NUM_HSPHY_TUNING_PARAMS]; }; +static int qcom_snps_hsphy_clk_init(struct qcom_snps_hsphy *hsphy) +{ + struct device *dev = hsphy->dev; + + hsphy->num_clks = 2; + hsphy->clks = devm_kcalloc(dev, hsphy->num_clks, sizeof(*hsphy->clks), GFP_KERNEL); + if (!hsphy->clks) + return -ENOMEM; + + /* + * TODO: Currently no device tree instantiation of the PHY is using the clock. + * This needs to be fixed in order for this code to be able to use devm_clk_bulk_get(). + */ + hsphy->clks[0].id = "cfg_ahb"; + hsphy->clks[0].clk = devm_clk_get_optional(dev, "cfg_ahb"); + if (IS_ERR(hsphy->clks[0].clk)) + return dev_err_probe(dev, PTR_ERR(hsphy->clks[0].clk), + "failed to get cfg_ahb clk\n"); + + hsphy->clks[1].id = "ref"; + hsphy->clks[1].clk = devm_clk_get(dev, "ref"); + if (IS_ERR(hsphy->clks[1].clk)) + return dev_err_probe(dev, PTR_ERR(hsphy->clks[1].clk), + "failed to get ref clk\n"); + + return 0; +} + static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset, u32 mask, u32 val) { @@ -365,16 +397,16 @@ static int qcom_snps_hsphy_init(struct phy *phy) if (ret) return ret; - ret = clk_prepare_enable(hsphy->cfg_ahb_clk); + ret = clk_bulk_prepare_enable(hsphy->num_clks, hsphy->clks); if (ret) { - dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); + dev_err(&phy->dev, "failed to enable clocks, %d\n", ret); goto poweroff_phy; } ret = reset_control_assert(hsphy->phy_reset); if (ret) { dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret); - goto disable_ahb_clk; + goto disable_clks; } usleep_range(100, 150); @@ -382,7 +414,7 @@ static int qcom_snps_hsphy_init(struct phy *phy) ret = reset_control_deassert(hsphy->phy_reset); if (ret) { dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret); - goto disable_ahb_clk; + goto disable_clks; } qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0, @@ -439,8 +471,8 @@ static int qcom_snps_hsphy_init(struct phy *phy) return 0; -disable_ahb_clk: - clk_disable_unprepare(hsphy->cfg_ahb_clk); +disable_clks: + clk_bulk_disable_unprepare(hsphy->num_clks, hsphy->clks); poweroff_phy: regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); @@ -452,7 +484,7 @@ static int qcom_snps_hsphy_exit(struct phy *phy) struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy); reset_control_assert(hsphy->phy_reset); - clk_disable_unprepare(hsphy->cfg_ahb_clk); + clk_bulk_disable_unprepare(hsphy->num_clks, hsphy->clks); regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); hsphy->phy_initialized = false; @@ -545,14 +577,15 @@ static int qcom_snps_hsphy_probe(struct platform_device *pdev) if (!hsphy) return -ENOMEM; + hsphy->dev = dev; + hsphy->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(hsphy->base)) return PTR_ERR(hsphy->base); - hsphy->ref_clk = devm_clk_get(dev, "ref"); - if (IS_ERR(hsphy->ref_clk)) - return dev_err_probe(dev, PTR_ERR(hsphy->ref_clk), - "failed to get ref clk\n"); + ret = qcom_snps_hsphy_clk_init(hsphy); + if (ret) + return dev_err_probe(dev, ret, "failed to initialize clocks\n"); hsphy->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL); if (IS_ERR(hsphy->phy_reset)) {