| Message ID | 20230718061052.1332993-3-bhupesh.sharma@linaro.org (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Add Qualcomm SM6115 / SM4250 EUD dt-bindings & driver support | expand |
On 18/07/2023 08:10, Bhupesh Sharma wrote: > On some SoCs (like the SM6115 / SM4250 SoC), the enable bit inside > 'tcsr_check_reg' needs to be set first to 'enable' EUD mode. > > So introduce a vendor-specific dt-property 'qcom,secure-eud-reg' > which specifies the base address of the TCSR reg space and the offset > of the 'tcsr_check_reg'. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml index f2c5ec7e6437b..ca38d219e57d5 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml @@ -45,6 +45,14 @@ properties: $ref: /schemas/graph.yaml#/properties/port description: This port is to be attached to the type C connector. + qcom,secure-eud-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to TCSR hardware block + - description: offset of the secure mode manager register + description: TCSR hardware block + required: - compatible - reg
On some SoCs (like the SM6115 / SM4250 SoC), the enable bit inside 'tcsr_check_reg' needs to be set first to 'enable' EUD mode. So introduce a vendor-specific dt-property 'qcom,secure-eud-reg' which specifies the base address of the TCSR reg space and the offset of the 'tcsr_check_reg'. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> --- Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml | 8 ++++++++ 1 file changed, 8 insertions(+)