| Message ID | 20230812112534.8610-7-a39.skl@gmail.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 31c133b4a07e3db456a7e661c96653cd65a25bc6 |
| Headers | show |
| Series | MSM8976 PLL,RPMPD and DTS changes | expand |
diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index ab76806317a7..7385d5edec04 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -338,7 +338,12 @@ mpss_mem: mpss@86c00000 { }; lpass_mem: lpass@8c200000 { - reg = <0x0 0x8c200000 0x0 0x1800000>; + reg = <0x0 0x8c200000 0x0 0x1000000>; + no-map; + }; + + wcnss_fw_mem: wcnss@8d200000 { + reg = <0x0 0x8d200000 0x0 0x800000>; no-map; };
MSM8976 downstream dts define reloc region which is used by pil-tz to load both wcnss and lpass, on mainline however we might not be able to do it and we need separate regions(also validating dts might get problematic if we had to put memory-region(rproc node) per device). Luckily it seems size and entry points in firmware headers appears to be static across multiple devices including Sony Loire platform and Xiaomi Redmi Note 3 Pro this should let us fit in first ~17MB Split lpass region(reloc on downstream) into two separate regions. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)