diff mbox series

[V1,2/2] arm64: dts: qcom: sc7280: Add UFS host controller and phy nodes

Message ID 20230821094937.13059-3-quic_nitirawa@quicinc.com (mailing list archive)
State Superseded
Headers show
Series Add UFS host controller and Phy nodes for sc7280 | expand

Commit Message

Nitin Rawat Aug. 21, 2023, 9:49 a.m. UTC 
Add UFS host controller and PHY nodes for sc7280.

Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 19 +++++++
 arch/arm64/boot/dts/qcom/sc7280.dtsi     | 64 ++++++++++++++++++++++++
 2 files changed, 83 insertions(+)

--
2.17.1

Comments

Manivannan Sadhasivam Aug. 22, 2023, 7:08 a.m. UTC | #1 
On Mon, Aug 21, 2023 at 03:19:37PM +0530, Nitin Rawat wrote:
> Add UFS host controller and PHY nodes for sc7280.
> 

You should split this patch into 2. One for SoC and another for board.

> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 19 +++++++
>  arch/arm64/boot/dts/qcom/sc7280.dtsi     | 64 ++++++++++++++++++++++++
>  2 files changed, 83 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> index 2ff549f4dc7a..c60cdd511222 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> @@ -451,6 +451,25 @@
>  	status = "okay";
>  };
> 
> +&ufs_mem_hc {
> +	reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
> +	vcc-supply = <&vreg_l7b_2p9>;
> +	vcc-max-microamp = <800000>;
> +	vccq-supply = <&vreg_l9b_1p2>;
> +	vccq-max-microamp = <900000>;
> +	vccq2-supply = <&vreg_l9b_1p2>;
> +	vccq2-max-microamp = <900000>;
> +
> +	status = "okay";
> +};
> +
> +&ufs_mem_phy {
> +	vdda-phy-supply = <&vreg_l10c_0p8>;
> +	vdda-pll-supply = <&vreg_l6b_1p2>;
> +
> +	status = "okay";
> +};
> +
>  &sdhc_1 {
>  	status = "okay";
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 925428a5f6ae..d4a15d56b384 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -908,6 +908,70 @@
>  			};
>  		};
> 
> +		ufs_mem_phy: phy@1d87000 {

Please sort the nodes in ascending order.

> +			compatible = "qcom,sc7280-qmp-ufs-phy";
> +			reg = <0x0 0x01d87000 0x0 0xe00>;
> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> +				 <&gcc GCC_UFS_1_CLKREF_EN>;
> +			clock-names = "ref", "ref_aux", "qref";
> +
> +			resets = <&ufs_mem_hc 0>;
> +			reset-names = "ufsphy";
> +
> +			#clock-cells = <1>;
> +			#phy-cells = <0>;
> +
> +			status = "disabled";
> +
> +		};
> +
> +		ufs_mem_hc: ufs@1d84000 {
> +			compatible = "qcom,sc7280-ufshc", "qcom,ufshc",
> +				     "jedec,ufs-2.0";
> +			reg = <0x0 0x01d84000 0x0 0x3000>;
> +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> +			phys = <&ufs_mem_phy>;
> +			phy-names = "ufsphy";
> +			lanes-per-direction = <2>;
> +			#reset-cells = <1>;
> +			resets = <&gcc GCC_UFS_PHY_BCR>;
> +			reset-names = "rst";
> +
> +			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
> +			required-opps = <&rpmhpd_opp_nom>;
> +
> +			iommus = <&apps_smmu 0x80 0x0>;
> +			dma-coherent;
> +
> +			clock-names = "core_clk",
> +				      "bus_aggr_clk",
> +				      "iface_clk",
> +				      "core_clk_unipro",
> +				      "ref_clk",
> +				      "tx_lane0_sync_clk",
> +				      "rx_lane0_sync_clk",
> +				      "rx_lane1_sync_clk";

"clocks" property should come first.

- Mani

> +			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
> +				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> +				 <&gcc GCC_UFS_PHY_AHB_CLK>,
> +				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> +				 <&rpmhcc RPMH_CXO_CLK>,
> +				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> +				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> +				 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> +			freq-table-hz =
> +				<75000000 300000000>,
> +				<0 0>,
> +				<0 0>,
> +				<75000000 300000000>,
> +				<0 0>,
> +				<0 0>,
> +				<0 0>,
> +				<0 0>;
> +			status = "disabled";
> +		};
> +
>  		sdhc_1: mmc@7c4000 {
>  			compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
>  			pinctrl-names = "default", "sleep";
> --
> 2.17.1
>
Nitin Rawat Sept. 26, 2023, 4:24 p.m. UTC | #2 
On 8/22/2023 12:38 PM, Manivannan Sadhasivam wrote:
> On Mon, Aug 21, 2023 at 03:19:37PM +0530, Nitin Rawat wrote:
>> Add UFS host controller and PHY nodes for sc7280.
>>
> 
> You should split this patch into 2. One for SoC and another for board.
Updated in Latest Patchset.

> 
>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 19 +++++++
>>   arch/arm64/boot/dts/qcom/sc7280.dtsi     | 64 ++++++++++++++++++++++++
>>   2 files changed, 83 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
>> index 2ff549f4dc7a..c60cdd511222 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
>> @@ -451,6 +451,25 @@
>>   	status = "okay";
>>   };
>>
>> +&ufs_mem_hc {
>> +	reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
>> +	vcc-supply = <&vreg_l7b_2p9>;
>> +	vcc-max-microamp = <800000>;
>> +	vccq-supply = <&vreg_l9b_1p2>;
>> +	vccq-max-microamp = <900000>;
>> +	vccq2-supply = <&vreg_l9b_1p2>;
>> +	vccq2-max-microamp = <900000>;
>> +
>> +	status = "okay";
>> +};
>> +
>> +&ufs_mem_phy {
>> +	vdda-phy-supply = <&vreg_l10c_0p8>;
>> +	vdda-pll-supply = <&vreg_l6b_1p2>;
>> +
>> +	status = "okay";
>> +};
>> +
>>   &sdhc_1 {
>>   	status = "okay";
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 925428a5f6ae..d4a15d56b384 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -908,6 +908,70 @@
>>   			};
>>   		};
>>
>> +		ufs_mem_phy: phy@1d87000 {
> 
> Please sort the nodes in ascending order.
Updated in Latest Patchset.

> 
>> +			compatible = "qcom,sc7280-qmp-ufs-phy";
>> +			reg = <0x0 0x01d87000 0x0 0xe00>;
>> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
>> +				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>> +				 <&gcc GCC_UFS_1_CLKREF_EN>;
>> +			clock-names = "ref", "ref_aux", "qref";
>> +
>> +			resets = <&ufs_mem_hc 0>;
>> +			reset-names = "ufsphy";
>> +
>> +			#clock-cells = <1>;
>> +			#phy-cells = <0>;
>> +
>> +			status = "disabled";
>> +
>> +		};
>> +
>> +		ufs_mem_hc: ufs@1d84000 {
>> +			compatible = "qcom,sc7280-ufshc", "qcom,ufshc",
>> +				     "jedec,ufs-2.0";
>> +			reg = <0x0 0x01d84000 0x0 0x3000>;
>> +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
>> +			phys = <&ufs_mem_phy>;
>> +			phy-names = "ufsphy";
>> +			lanes-per-direction = <2>;
>> +			#reset-cells = <1>;
>> +			resets = <&gcc GCC_UFS_PHY_BCR>;
>> +			reset-names = "rst";
>> +
>> +			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
>> +			required-opps = <&rpmhpd_opp_nom>;
>> +
>> +			iommus = <&apps_smmu 0x80 0x0>;
>> +			dma-coherent;
>> +
>> +			clock-names = "core_clk",
>> +				      "bus_aggr_clk",
>> +				      "iface_clk",
>> +				      "core_clk_unipro",
>> +				      "ref_clk",
>> +				      "tx_lane0_sync_clk",
>> +				      "rx_lane0_sync_clk",
>> +				      "rx_lane1_sync_clk";
> 
> "clocks" property should come first.
  DT binding shows clock-names first followed by clocks.
  Let me know if see still see concern, would update .

> 
> - Mani
> 
>> +			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
>> +				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
>> +				 <&gcc GCC_UFS_PHY_AHB_CLK>,
>> +				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
>> +				 <&rpmhcc RPMH_CXO_CLK>,
>> +				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
>> +				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
>> +				 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
>> +			freq-table-hz =
>> +				<75000000 300000000>,
>> +				<0 0>,
>> +				<0 0>,
>> +				<75000000 300000000>,
>> +				<0 0>,
>> +				<0 0>,
>> +				<0 0>,
>> +				<0 0>;
>> +			status = "disabled";
>> +		};
>> +
>>   		sdhc_1: mmc@7c4000 {
>>   			compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
>>   			pinctrl-names = "default", "sleep";
>> --
>> 2.17.1
>>
> 

Thanks,
Nitin
Konrad Dybcio Sept. 26, 2023, 5:29 p.m. UTC | #3 
On 26.09.2023 18:24, Nitin Rawat wrote:
> 
> 
> On 8/22/2023 12:38 PM, Manivannan Sadhasivam wrote:
>> On Mon, Aug 21, 2023 at 03:19:37PM +0530, Nitin Rawat wrote:
>>> Add UFS host controller and PHY nodes for sc7280.
>>>
>>
>> You should split this patch into 2. One for SoC and another for board.
> Updated in Latest Patchset.
> 
>>
>>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
>>> ---
>>>   arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 19 +++++++
>>>   arch/arm64/boot/dts/qcom/sc7280.dtsi     | 64 ++++++++++++++++++++++++
>>>   2 files changed, 83 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
>>> index 2ff549f4dc7a..c60cdd511222 100644
>>> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
>>> @@ -451,6 +451,25 @@
>>>       status = "okay";
>>>   };
>>>
>>> +&ufs_mem_hc {
>>> +    reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
>>> +    vcc-supply = <&vreg_l7b_2p9>;
>>> +    vcc-max-microamp = <800000>;
>>> +    vccq-supply = <&vreg_l9b_1p2>;
>>> +    vccq-max-microamp = <900000>;
>>> +    vccq2-supply = <&vreg_l9b_1p2>;
>>> +    vccq2-max-microamp = <900000>;
>>> +
>>> +    status = "okay";
>>> +};
>>> +
>>> +&ufs_mem_phy {
>>> +    vdda-phy-supply = <&vreg_l10c_0p8>;
>>> +    vdda-pll-supply = <&vreg_l6b_1p2>;
>>> +
>>> +    status = "okay";
>>> +};
>>> +
>>>   &sdhc_1 {
>>>       status = "okay";
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> index 925428a5f6ae..d4a15d56b384 100644
>>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> @@ -908,6 +908,70 @@
>>>               };
>>>           };
>>>
>>> +        ufs_mem_phy: phy@1d87000 {
>>
>> Please sort the nodes in ascending order.
> Updated in Latest Patchset.
> 
>>
>>> +            compatible = "qcom,sc7280-qmp-ufs-phy";
>>> +            reg = <0x0 0x01d87000 0x0 0xe00>;
>>> +            clocks = <&rpmhcc RPMH_CXO_CLK>,
>>> +                 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>>> +                 <&gcc GCC_UFS_1_CLKREF_EN>;
>>> +            clock-names = "ref", "ref_aux", "qref";
>>> +
>>> +            resets = <&ufs_mem_hc 0>;
>>> +            reset-names = "ufsphy";
>>> +
>>> +            #clock-cells = <1>;
>>> +            #phy-cells = <0>;
>>> +
>>> +            status = "disabled";
>>> +
>>> +        };
>>> +
>>> +        ufs_mem_hc: ufs@1d84000 {
>>> +            compatible = "qcom,sc7280-ufshc", "qcom,ufshc",
>>> +                     "jedec,ufs-2.0";
>>> +            reg = <0x0 0x01d84000 0x0 0x3000>;
>>> +            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
>>> +            phys = <&ufs_mem_phy>;
>>> +            phy-names = "ufsphy";
>>> +            lanes-per-direction = <2>;
>>> +            #reset-cells = <1>;
>>> +            resets = <&gcc GCC_UFS_PHY_BCR>;
>>> +            reset-names = "rst";
>>> +
>>> +            power-domains = <&gcc GCC_UFS_PHY_GDSC>;
>>> +            required-opps = <&rpmhpd_opp_nom>;
>>> +
>>> +            iommus = <&apps_smmu 0x80 0x0>;
>>> +            dma-coherent;
>>> +
>>> +            clock-names = "core_clk",
>>> +                      "bus_aggr_clk",
>>> +                      "iface_clk",
>>> +                      "core_clk_unipro",
>>> +                      "ref_clk",
>>> +                      "tx_lane0_sync_clk",
>>> +                      "rx_lane0_sync_clk",
>>> +                      "rx_lane1_sync_clk";
>>
>> "clocks" property should come first.
>  DT binding shows clock-names first followed by clocks.
>  Let me know if see still see concern, would update .
The dt bindings example is rarely useful.. perhaps we should
change that..

The general consensus there is to have

property
property-names

Konrad
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 2ff549f4dc7a..c60cdd511222 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -451,6 +451,25 @@ 
 	status = "okay";
 };

+&ufs_mem_hc {
+	reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+	vcc-supply = <&vreg_l7b_2p9>;
+	vcc-max-microamp = <800000>;
+	vccq-supply = <&vreg_l9b_1p2>;
+	vccq-max-microamp = <900000>;
+	vccq2-supply = <&vreg_l9b_1p2>;
+	vccq2-max-microamp = <900000>;
+
+	status = "okay";
+};
+
+&ufs_mem_phy {
+	vdda-phy-supply = <&vreg_l10c_0p8>;
+	vdda-pll-supply = <&vreg_l6b_1p2>;
+
+	status = "okay";
+};
+
 &sdhc_1 {
 	status = "okay";

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 925428a5f6ae..d4a15d56b384 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -908,6 +908,70 @@ 
 			};
 		};

+		ufs_mem_phy: phy@1d87000 {
+			compatible = "qcom,sc7280-qmp-ufs-phy";
+			reg = <0x0 0x01d87000 0x0 0xe00>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+				 <&gcc GCC_UFS_1_CLKREF_EN>;
+			clock-names = "ref", "ref_aux", "qref";
+
+			resets = <&ufs_mem_hc 0>;
+			reset-names = "ufsphy";
+
+			#clock-cells = <1>;
+			#phy-cells = <0>;
+
+			status = "disabled";
+
+		};
+
+		ufs_mem_hc: ufs@1d84000 {
+			compatible = "qcom,sc7280-ufshc", "qcom,ufshc",
+				     "jedec,ufs-2.0";
+			reg = <0x0 0x01d84000 0x0 0x3000>;
+			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&ufs_mem_phy>;
+			phy-names = "ufsphy";
+			lanes-per-direction = <2>;
+			#reset-cells = <1>;
+			resets = <&gcc GCC_UFS_PHY_BCR>;
+			reset-names = "rst";
+
+			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			iommus = <&apps_smmu 0x80 0x0>;
+			dma-coherent;
+
+			clock-names = "core_clk",
+				      "bus_aggr_clk",
+				      "iface_clk",
+				      "core_clk_unipro",
+				      "ref_clk",
+				      "tx_lane0_sync_clk",
+				      "rx_lane0_sync_clk",
+				      "rx_lane1_sync_clk";
+			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>,
+				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+				 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+			freq-table-hz =
+				<75000000 300000000>,
+				<0 0>,
+				<0 0>,
+				<75000000 300000000>,
+				<0 0>,
+				<0 0>,
+				<0 0>,
+				<0 0>;
+			status = "disabled";
+		};
+
 		sdhc_1: mmc@7c4000 {
 			compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
 			pinctrl-names = "default", "sleep";