From patchwork Wed Aug 30 22:48:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 13370780 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 247C1C83F19 for ; Wed, 30 Aug 2023 22:50:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343840AbjH3Wum (ORCPT ); Wed, 30 Aug 2023 18:50:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343996AbjH3Wuj (ORCPT ); Wed, 30 Aug 2023 18:50:39 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 317DFE52; Wed, 30 Aug 2023 15:50:12 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37ULcmWV030051; Wed, 30 Aug 2023 22:49:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=Hhgz8geUToeCvo4hHkI6mfD0yLiUJl04ysXctROHs4E=; b=MQPN+TffPcHEmw9/tqf4NqxAcTACwGNKMWmPRex1rDwm9qYCugJp47Y6AQNCp8ksXWE2 AMZXHm+LGAPJ7IAf0RaJU3vF7Xb3LA5P3HJ2PyuQIZA+kO0yAZdBl4EQBVIJTvGyqP9A xNgpx4OsBiNJeTOEGQnE0zC0BOUKfdleYJV6dF77hsxXfmQB5ZUPpktOtilM8+BgxAXm TkDcn0+QPv5l02Skvdx8IufAPOvKYfIFheHECVs15Y2GyBW/wAzUFHJL1KxXSu+61o48 7IC+gIh/KI9oFKTVqCIEA3ZVv+/vTUHu2vSZh7qZTU1vw2WYhfbdLR/hk4mCeM1umRDX yA== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3st159ssdy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Aug 2023 22:49:48 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 37UMnlBQ009092 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Aug 2023 22:49:47 GMT Received: from abhinavk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Wed, 30 Aug 2023 15:49:46 -0700 From: Abhinav Kumar To: , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Daniel Vetter" CC: , , , , , Subject: [PATCH 02/16] drm/msm/dpu: add formats check for writeback encoder Date: Wed, 30 Aug 2023 15:48:55 -0700 Message-ID: <20230830224910.8091-3-quic_abhinavk@quicinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230830224910.8091-1-quic_abhinavk@quicinc.com> References: <20230830224910.8091-1-quic_abhinavk@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: IGv3iUtcwrh_PCHd0C6fLHUIwUod7wbn X-Proofpoint-GUID: IGv3iUtcwrh_PCHd0C6fLHUIwUod7wbn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-30_18,2023-08-29_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 mlxscore=0 suspectscore=0 spamscore=0 mlxlogscore=892 priorityscore=1501 clxscore=1015 bulkscore=0 impostorscore=0 malwarescore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2308300207 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In preparation of adding more formats to dpu writeback add format validation to it to fail any unsupported formats. Fixes: d7d0e73f7de3 ("drm/msm/dpu: introduce the dpu_encoder_phys_* for writeback") Signed-off-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index 284a88060221..6a1f8e34f18a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -238,6 +238,7 @@ static int dpu_encoder_phys_wb_atomic_check( { struct drm_framebuffer *fb; const struct drm_display_mode *mode = &crtc_state->mode; + int ret; DPU_DEBUG("[atomic_check:%d, \"%s\",%d,%d]\n", phys_enc->hw_wb->idx, mode->name, mode->hdisplay, mode->vdisplay); @@ -274,6 +275,12 @@ static int dpu_encoder_phys_wb_atomic_check( return -EINVAL; } + ret = drm_atomic_helper_check_wb_encoder_state(phys_enc->parent, conn_state); + if (ret < 0) { + DPU_ERROR("invalid pixel format %p4cc\n", &fb->format->format); + return ret; + } + return 0; }