| Message ID | 20230913153529.32777-2-bartosz.golaszewski@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 96272ba7103d4518e2d0f17daf6fe0008fc6e12c |
| Headers | show |
| Series | [1/2] dt-bindings: crypto: ice: document the sa8775p inline crypto engine | expand |
On 13.09.2023 17:35, Bartosz Golaszewski wrote: > Add an ICE node to sa8775p SoC description and enable it by adding a > phandle to the UFS node. > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > --- I don't have any sources backing this up, but 8350 seems to have the exact same register ranges for this block, so I'm inclined to believe it's ok Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 9f4f58e831a4..b6a93b11cbbd 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -1525,6 +1525,7 @@ ufs_mem_hc: ufs@1d84000 { <0 0>, <0 0>, <0 0>; + qcom,ice = <&ice>; status = "disabled"; }; @@ -1546,6 +1547,13 @@ ufs_mem_phy: phy@1d87000 { status = "disabled"; }; + ice: crypto@1d88000 { + compatible = "qcom,sa8775p-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x0 0x01d88000 0x0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + usb_0_hsphy: phy@88e4000 { compatible = "qcom,sa8775p-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy";
Add an ICE node to sa8775p SoC description and enable it by adding a phandle to the UFS node. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)