| Message ID | 20230928133312.11371-3-quic_kbajaj@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Initial support for the QCM6490 IDP | expand |
On 28.09.2023 15:33, Komal Bajaj wrote: > Add qcm6490 devicetree file for QCM6490 SoC and QCM6490 IDP > platform. QCM6490 is derived from SC7280 meant for various > form factor including IoT. > > Supported features are, as of now: > * Debug UART > * eMMC > * USB > > Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> > --- [...] > +/ { > + model = "Qualcomm Technologies, Inc. QCM6490 IDP platform"; Isomething Development Platform platform? > + compatible = "qcom,qcm6490-idp", "qcom,qcm6490"; > + > + aliases { > + serial0 = &uart5; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > +}; Stray newline above > + > +&apps_rsc { > + regulators-0 { > + compatible = "qcom,pm7325-rpmh-regulators"; > + qcom,pmic-id = "b"; > + > + vreg_s1b_1p8: smps1 { > + regulator-min-microvolt = <1856000>; > + regulator-max-microvolt = <2040000>; Hm, you didn't specify regulator-initial-mode on any vregs [...] > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/qcm6490.dtsi > @@ -0,0 +1,137 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include "sc7280.dtsi" > + > +/* > + * Delete sc7280 lpass related nodes as qcm6490 intends to move away from > + * bypass configuration > + */ > +/delete-node/ &lpass_ag_noc; > +/delete-node/ &lpass_aon; > +/delete-node/ &lpass_audiocc; > +/delete-node/ &lpass_core; > +/delete-node/ &lpass_cpu; > +/delete-node/ &lpass_hm; > +/delete-node/ &lpass_rx_macro; > +/delete-node/ &lpass_tx_macro; > +/delete-node/ &lpass_va_macro; > +/delete-node/ &lpass_tlmm; > +/delete-node/ &lpasscc; > +/delete-node/ &swr0; > +/delete-node/ &swr1; That's very unnecessary, most of these nodes are in use even when routing audio through ADSP. Ones that are not, are set to status = "reserved" and some will need more work to function based on the configuration. There was once a series from somebody at qc to introduce ADSP audio on 7280, but it was full of hacks and NAKed > + > +/* > + * Delete unused sc7280 memory nodes and define the memory regions > + * required by qcm6490 > + */ That's specific to your board. > +/delete-node/ &rmtfs_mem; > +/delete-node/ &wlan_ce_mem; > + > +/{ > + reserved-memory { > + secdata_apss_mem: secdata-apss@808ff000 { > + reg = <0x0 0x808ff000 0x0 0x1000>; > + no-map; > + }; This is identical to the entry in sc7280.dtsi. > + > + cdsp_secure_heap_mem: cdsp-secure-heap@81800000 { > + reg = <0x0 0x81800000 0x0 0x1e00000>; > + no-map; > + }; > + > + camera_mem: camera@84300000 { > + reg = <0x0 0x84300000 0x0 0x500000>; > + no-map; > + }; > + > + adsp_mem: adsp@86100000 { > + reg = <0x0 0x86100000 0x0 0x2800000>; > + no-map; > + }; > + > + cdsp_mem: cdsp@88900000 { > + reg = <0x0 0x88900000 0x0 0x1e00000>; > + no-map; > + }; > + > + cvp_mem: cvp@8ac00000 { > + reg = <0x0 0x8ac00000 0x0 0x500000>; > + no-map; > + }; > + > + ipa_gsi_mem: ipa-gsi@8b110000 { > + reg = <0x0 0x8b110000 0x0 0xa000>; > + no-map; > + }; > + > + gpu_microcode_mem: gpu-microcode@8b11a000 { > + reg = <0x0 0x8b11a000 0x0 0x2000>; > + no-map; > + }; > + > + mpss_mem: mpss@8b800000 { > + reg = <0x0 0x8b800000 0x0 0xf600000>; > + no-map; > + }; > + > + wpss_mem: wpss@9ae00000 { > + reg = <0x0 0x9ae00000 0x0 0x1900000>; > + no-map; > + }; This entry is in both chrome-common and fairphone (meaning all boards use it), perhaps this one could be moved to 7280.dtsi > + > + tz_stat_mem: tz-stat@c0000000 { > + reg = <0x0 0xc0000000 0x0 0x100000>; > + no-map; > + }; > + > + tags_mem: tags@c0100000 { > + reg = <0x0 0xc0100000 0x0 0x1200000>; > + no-map; > + }; > + > + qtee_mem: qtee@c1300000 { > + reg = <0x0 0xc1300000 0x0 0x500000>; > + no-map; > + }; > + > + trusted_apps_mem: trusted_apps@c1800000 { > + reg = <0x0 0xc1800000 0x0 0x3900000>; > + no-map; > + }; > + }; > +}; > + > +&hyp_mem { > + reg = <0x0 0x80000000 0x0 0x600000>; This is identical to the entry in sc7280.dtsi. > +}; > + > +&mpss_mem { > + reg = <0x0 0x8b800000 0x0 0xf600000>; You're defining it here and overwriting it with an identical value. Looks like CrOS folks don't boot up the modem on non-LTE SKUs. Weird. Normally it would host some more software.. > +}; > + > +&remoteproc_mpss { > + memory-region = <&mpss_mem>; This is identical to the entry in sc7280.dtsi. > +}; > + > +&video_mem { > + reg = <0x0 0x8a700000 0x0 0x500000>; > +}; > + > +&wifi { > + memory-region = <&wlan_fw_mem>; No CE region? > +}; > + > +&wlan_fw_mem { > + reg = <0x0 0x80c00000 0x0 0xc00000>; This is identical to the entry in sc7280.dtsi. The memory map generally looks quite different to both chrome and fairphone.. are you sure it's all correct? Konrad
On 9/28/2023 7:16 PM, Konrad Dybcio wrote: > On 28.09.2023 15:33, Komal Bajaj wrote: >> Add qcm6490 devicetree file for QCM6490 SoC and QCM6490 IDP >> platform. QCM6490 is derived from SC7280 meant for various >> form factor including IoT. >> >> Supported features are, as of now: >> * Debug UART >> * eMMC >> * USB >> >> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> >> --- > [...] > >> +/ { >> + model = "Qualcomm Technologies, Inc. QCM6490 IDP platform"; > Isomething Development Platform platform? Will drop suffix platform. > >> + compatible = "qcom,qcm6490-idp", "qcom,qcm6490"; >> + >> + aliases { >> + serial0 = &uart5; >> + }; >> + >> + chosen { >> + stdout-path = "serial0:115200n8"; >> + }; >> + >> +}; > Stray newline above Noted. > >> + >> +&apps_rsc { >> + regulators-0 { >> + compatible = "qcom,pm7325-rpmh-regulators"; >> + qcom,pmic-id = "b"; >> + >> + vreg_s1b_1p8: smps1 { >> + regulator-min-microvolt = <1856000>; >> + regulator-max-microvolt = <2040000>; > Hm, you didn't specify regulator-initial-mode on any vregs Okay, will specify it in next patchset. > > [...] > >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/qcm6490.dtsi >> @@ -0,0 +1,137 @@ >> +// SPDX-License-Identifier: BSD-3-Clause >> +/* >> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. >> + */ >> + >> +#include "sc7280.dtsi" >> + >> +/* >> + * Delete sc7280 lpass related nodes as qcm6490 intends to move away from >> + * bypass configuration >> + */ >> +/delete-node/ &lpass_ag_noc; >> +/delete-node/ &lpass_aon; >> +/delete-node/ &lpass_audiocc; >> +/delete-node/ &lpass_core; >> +/delete-node/ &lpass_cpu; >> +/delete-node/ &lpass_hm; >> +/delete-node/ &lpass_rx_macro; >> +/delete-node/ &lpass_tx_macro; >> +/delete-node/ &lpass_va_macro; >> +/delete-node/ &lpass_tlmm; >> +/delete-node/ &lpasscc; >> +/delete-node/ &swr0; >> +/delete-node/ &swr1; > That's very unnecessary, most of these nodes are in use even > when routing audio through ADSP. > > Ones that are not, are set to status = "reserved" and some > will need more work to function based on the configuration. > > There was once a series from somebody at qc to introduce ADSP > audio on 7280, but it was full of hacks and NAKed Seeking clarification which nodes will be used and which should be disabled. For now, will remove it. > > >> + >> +/* >> + * Delete unused sc7280 memory nodes and define the memory regions >> + * required by qcm6490 >> + */ > That's specific to your board. No, these are not board specific, it's soc specific. > >> +/delete-node/ &rmtfs_mem; >> +/delete-node/ &wlan_ce_mem; >> + >> +/{ >> + reserved-memory { >> + secdata_apss_mem: secdata-apss@808ff000 { >> + reg = <0x0 0x808ff000 0x0 0x1000>; >> + no-map; >> + }; > This is identical to the entry in sc7280.dtsi. Yeah, right. Will remove it. > >> + >> + cdsp_secure_heap_mem: cdsp-secure-heap@81800000 { >> + reg = <0x0 0x81800000 0x0 0x1e00000>; >> + no-map; >> + }; >> + >> + camera_mem: camera@84300000 { >> + reg = <0x0 0x84300000 0x0 0x500000>; >> + no-map; >> + }; >> + >> + adsp_mem: adsp@86100000 { >> + reg = <0x0 0x86100000 0x0 0x2800000>; >> + no-map; >> + }; >> + >> + cdsp_mem: cdsp@88900000 { >> + reg = <0x0 0x88900000 0x0 0x1e00000>; >> + no-map; >> + }; >> + >> + cvp_mem: cvp@8ac00000 { >> + reg = <0x0 0x8ac00000 0x0 0x500000>; >> + no-map; >> + }; >> + >> + ipa_gsi_mem: ipa-gsi@8b110000 { >> + reg = <0x0 0x8b110000 0x0 0xa000>; >> + no-map; >> + }; >> + >> + gpu_microcode_mem: gpu-microcode@8b11a000 { >> + reg = <0x0 0x8b11a000 0x0 0x2000>; >> + no-map; >> + }; >> + >> + mpss_mem: mpss@8b800000 { >> + reg = <0x0 0x8b800000 0x0 0xf600000>; >> + no-map; >> + }; >> + >> + wpss_mem: wpss@9ae00000 { >> + reg = <0x0 0x9ae00000 0x0 0x1900000>; >> + no-map; >> + }; > This entry is in both chrome-common and fairphone (meaning all boards > use it), perhaps this one could be moved to 7280.dtsi Missed to update region for wpss_mem. It's different what's used in chrome-common and fairphone. > >> + >> + tz_stat_mem: tz-stat@c0000000 { >> + reg = <0x0 0xc0000000 0x0 0x100000>; >> + no-map; >> + }; >> + >> + tags_mem: tags@c0100000 { >> + reg = <0x0 0xc0100000 0x0 0x1200000>; >> + no-map; >> + }; >> + >> + qtee_mem: qtee@c1300000 { >> + reg = <0x0 0xc1300000 0x0 0x500000>; >> + no-map; >> + }; >> + >> + trusted_apps_mem: trusted_apps@c1800000 { >> + reg = <0x0 0xc1800000 0x0 0x3900000>; >> + no-map; >> + }; >> + }; >> +}; >> + >> +&hyp_mem { >> + reg = <0x0 0x80000000 0x0 0x600000>; > This is identical to the entry in sc7280.dtsi. Will remove it. > >> +}; >> + >> +&mpss_mem { >> + reg = <0x0 0x8b800000 0x0 0xf600000>; > You're defining it here and overwriting it with an identical > value. > > Looks like CrOS folks don't boot up the modem on non-LTE SKUs. > Weird. Normally it would host some more software.. > >> +}; >> + >> +&remoteproc_mpss { >> + memory-region = <&mpss_mem>; > This is identical to the entry in sc7280.dtsi. Will remove it. > >> +}; >> + >> +&video_mem { >> + reg = <0x0 0x8a700000 0x0 0x500000>; >> +}; >> + >> +&wifi { >> + memory-region = <&wlan_fw_mem>; > No CE region? Yes, no CE region is required here. > >> +}; >> + >> +&wlan_fw_mem { >> + reg = <0x0 0x80c00000 0x0 0xc00000>; > This is identical to the entry in sc7280.dtsi. Will remove it. > > > The memory map generally looks quite different to both chrome > and fairphone.. are you sure it's all correct? Yes, it's correct, it's different than chrome and fairphone. Thanks Komal > > Konrad
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 73c3be0f8872..3a2d9dbaacce 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -82,6 +82,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-fairphone-fp5.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts new file mode 100644 index 000000000000..7cd7d9f556ae --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> +#include "qcm6490.dtsi" +#include "pm7325.dtsi" +#include "pm8350c.dtsi" +#include "pmk8350.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCM6490 IDP platform"; + compatible = "qcom,qcm6490-idp", "qcom,qcm6490"; + + aliases { + serial0 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vreg_s1b_1p8: smps1 { + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7b_0p9: smps7 { + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + }; + + vreg_s8b_1p2: smps8 { + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1500000>; + }; + + vreg_l1b_0p8: ldo1 { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + }; + + vreg_l2b_3p0: ldo2 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + vreg_l6b_1p2: ldo6 { + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + }; + + vreg_l7b_2p9: ldo7 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + }; + + vreg_l8b_0p9: ldo8 { + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + }; + + vreg_l9b_1p2: ldo9 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l11b_1p7: ldo11 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_l12b_0p8: ldo12 { + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + }; + + vreg_l13b_0p8: ldo13 { + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <824000>; + }; + + vreg_l14b_1p2: ldo14 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l15b_0p8: ldo15 { + regulator-min-microvolt = <765000>; + regulator-max-microvolt = <1020000>; + }; + + vreg_l16b_1p2: ldo16 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + + vreg_l17b_1p8: ldo17 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + + vreg_l18b_1p8: ldo18 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_l19b_1p8: ldo19 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s1c_2p2: smps1 { + regulator-min-microvolt = <2190000>; + regulator-max-microvolt = <2210000>; + }; + + vreg_s9c_1p0: smps9 { + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + }; + + vreg_l2c_1p8: ldo2 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + vreg_l3c_3p0: ldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3540000>; + }; + + vreg_l4c_1p8: ldo4 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + }; + + vreg_l5c_1p8: ldo5 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + }; + + vreg_l6c_2p9: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_l9c_2p9: ldo9 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + }; + + vreg_l10c_0p8: ldo10 { + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + }; + + vreg_l11c_2p8: ldo11 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3544000>; + }; + + vreg_l12c_1p8: ldo12 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_l13c_3p0: ldo13 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + }; + }; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&sdhc_1 { + non-removable; + no-sd; + no-sdio; + + vmmc-supply = <&vreg_l7b_2p9>; + vqmmc-supply = <&vreg_l19b_1p8>; + + status = "okay"; +}; + +&uart5 { + compatible = "qcom,geni-debug-uart"; + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l10c_0p8>; + vdda33-supply = <&vreg_l2b_3p0>; + vdda18-supply = <&vreg_l1c_1p8>; + qcom,hs-rise-fall-time-bp = <0>; + qcom,squelch-detector-bp = <(-2090)>; + qcom,hs-disconnect-bp = <1743>; + qcom,hs-amplitude-bp = <1780>; + qcom,hs-crossover-voltage-microvolt = <(-31000)>; + qcom,hs-output-impedance-micro-ohms = <2600000>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l1b_0p8>; + + status = "okay"; +}; + +/* PINCTRL - additions to nodes defined in sc7280.dtsi */ + +&pm8350c_pwm { + status = "okay"; +}; + +&qup_uart5_tx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart5_rx { + drive-strength = <2>; + bias-pull-up; +}; + +&sdc1_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc1_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc1_data { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc1_rclk { + bias-pull-down; +}; diff --git a/arch/arm64/boot/dts/qcom/qcm6490.dtsi b/arch/arm64/boot/dts/qcom/qcm6490.dtsi new file mode 100644 index 000000000000..31f44fc87388 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcm6490.dtsi @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sc7280.dtsi" + +/* + * Delete sc7280 lpass related nodes as qcm6490 intends to move away from + * bypass configuration + */ +/delete-node/ &lpass_ag_noc; +/delete-node/ &lpass_aon; +/delete-node/ &lpass_audiocc; +/delete-node/ &lpass_core; +/delete-node/ &lpass_cpu; +/delete-node/ &lpass_hm; +/delete-node/ &lpass_rx_macro; +/delete-node/ &lpass_tx_macro; +/delete-node/ &lpass_va_macro; +/delete-node/ &lpass_tlmm; +/delete-node/ &lpasscc; +/delete-node/ &swr0; +/delete-node/ &swr1; + +/* + * Delete unused sc7280 memory nodes and define the memory regions + * required by qcm6490 + */ +/delete-node/ &rmtfs_mem; +/delete-node/ &wlan_ce_mem; + +/{ + reserved-memory { + secdata_apss_mem: secdata-apss@808ff000 { + reg = <0x0 0x808ff000 0x0 0x1000>; + no-map; + }; + + cdsp_secure_heap_mem: cdsp-secure-heap@81800000 { + reg = <0x0 0x81800000 0x0 0x1e00000>; + no-map; + }; + + camera_mem: camera@84300000 { + reg = <0x0 0x84300000 0x0 0x500000>; + no-map; + }; + + adsp_mem: adsp@86100000 { + reg = <0x0 0x86100000 0x0 0x2800000>; + no-map; + }; + + cdsp_mem: cdsp@88900000 { + reg = <0x0 0x88900000 0x0 0x1e00000>; + no-map; + }; + + cvp_mem: cvp@8ac00000 { + reg = <0x0 0x8ac00000 0x0 0x500000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@8b110000 { + reg = <0x0 0x8b110000 0x0 0xa000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode@8b11a000 { + reg = <0x0 0x8b11a000 0x0 0x2000>; + no-map; + }; + + mpss_mem: mpss@8b800000 { + reg = <0x0 0x8b800000 0x0 0xf600000>; + no-map; + }; + + wpss_mem: wpss@9ae00000 { + reg = <0x0 0x9ae00000 0x0 0x1900000>; + no-map; + }; + + tz_stat_mem: tz-stat@c0000000 { + reg = <0x0 0xc0000000 0x0 0x100000>; + no-map; + }; + + tags_mem: tags@c0100000 { + reg = <0x0 0xc0100000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: qtee@c1300000 { + reg = <0x0 0xc1300000 0x0 0x500000>; + no-map; + }; + + trusted_apps_mem: trusted_apps@c1800000 { + reg = <0x0 0xc1800000 0x0 0x3900000>; + no-map; + }; + }; +}; + +&hyp_mem { + reg = <0x0 0x80000000 0x0 0x600000>; +}; + +&mpss_mem { + reg = <0x0 0x8b800000 0x0 0xf600000>; +}; + +&remoteproc_mpss { + memory-region = <&mpss_mem>; +}; + +&video_mem { + reg = <0x0 0x8a700000 0x0 0x500000>; +}; + +&wifi { + memory-region = <&wlan_fw_mem>; +}; + +&wlan_fw_mem { + reg = <0x0 0x80c00000 0x0 0xc00000>; +}; + +&wpss_mem { + reg = <0x0 0x84800000 0x0 0x1900000>; +}; + +&xbl_mem { + reg = <0x0 0x80700000 0x0 0x100000>; +};
Add qcm6490 devicetree file for QCM6490 SoC and QCM6490 IDP platform. QCM6490 is derived from SC7280 meant for various form factor including IoT. Supported features are, as of now: * Debug UART * eMMC * USB Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 304 +++++++++++++++++++++++ arch/arm64/boot/dts/qcom/qcm6490.dtsi | 137 ++++++++++ 3 files changed, 442 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcm6490-idp.dts create mode 100644 arch/arm64/boot/dts/qcom/qcm6490.dtsi -- 2.42.0