From patchwork Thu Oct 12 05:45:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13418352 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EEEFCDB46E for ; Thu, 12 Oct 2023 05:46:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377358AbjJLFqa (ORCPT ); Thu, 12 Oct 2023 01:46:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377344AbjJLFqP (ORCPT ); Thu, 12 Oct 2023 01:46:15 -0400 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1367126 for ; Wed, 11 Oct 2023 22:45:57 -0700 (PDT) Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-69af8a42066so483745b3a.1 for ; Wed, 11 Oct 2023 22:45:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697089557; x=1697694357; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YTqO3Bk11vaIqEHJBs3qluSIAGA/bXfT2WWIycF5MX0=; b=CqWJFnSbX/X+rnflIIJydJ+aYEVKv+Dv0g8VF+SJPTO2D4zzEiYcatqwpYDG5cByYY 0XZa0OtmPh2ezyWTBGYrVXoEJPpZmH8wQkkO2dqZWaoBIaBlUJrO7tSnTcCdidpMKHGL IIALbJbLqsVdvjQaf0uwx60HoCnTDTWWnqiGNBDT8im8vPLXc/pBeYczQya+vJmEQgrV HuKHqNf5W8uo3D/96RUUX677x7qk/h/ydWtbfjBoSwhyLDcmONrDXIaCQDiNTv04hGRh LQKPL1E7X2bhAon32wtXF8eFRQN+93Ngj4gPnZWCXTZpPE7wXYU20X4TsXfpS1F7iUf7 U8Eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697089557; x=1697694357; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YTqO3Bk11vaIqEHJBs3qluSIAGA/bXfT2WWIycF5MX0=; b=MRJckxewZh6xvyvbVHag86tJ39QNducF69Lqq9OgJDYpzI4eOyS6u34d/OMGjOJdt0 bNt+L1/h++JNmLSIART+a21JqtinyYCRhIPQLeOsBdBK89W5dL1VVjzBGhVtZQ2NnZF3 qQmkicpre+PmN0t93momFnimqklCnhPVVcgV3Ts8pUwAjHg+5B6B1vlpsBY4JjOd4ZH+ Ik+VY6scxPuks0Q4YOg8WWDzpGGcKxitHIJ9WarV8g7sy4MTidqTw88arCmgm677VkIH 8LmoVRY4wM58RleQcGyboY0uL5DyX6DXkqUmVf7SGkKeqmXI2S7jMNf0GISfs5Vhn44s Sq4w== X-Gm-Message-State: AOJu0YxvrEBxhVw9CTVPALPFxHOCM7jz6T9yZLjX9ZYxt902dHTRHYo2 M/A3icAmyPLHv2uv0sM8q1KU X-Google-Smtp-Source: AGHT+IHO+5SbtId9L1+jaifztpi6kqaKVXfP+u0rJNVbTLYBDc+4gn3SGy40qi/57lYijfPh2FZmeA== X-Received: by 2002:a05:6a00:2409:b0:690:3b59:cc7b with SMTP id z9-20020a056a00240900b006903b59cc7bmr22476242pfh.32.1697089557098; Wed, 11 Oct 2023 22:45:57 -0700 (PDT) Received: from localhost.localdomain ([120.138.12.180]) by smtp.gmail.com with ESMTPSA id c5-20020a633505000000b0057cb5a780ebsm812396pga.76.2023.10.11.22.45.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 22:45:56 -0700 (PDT) From: Manivannan Sadhasivam To: vireshk@kernel.org, nm@ti.com, sboyd@kernel.org, myungjoo.ham@samsung.com, kyungmin.park@samsung.com, cw00.choi@samsung.com, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jejb@linux.ibm.com, martin.petersen@oracle.com Cc: alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, linux-scsi@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, quic_asutoshd@quicinc.com, quic_cang@quicinc.com, quic_nitirawa@quicinc.com, quic_narepall@quicinc.com, quic_bhaskarv@quicinc.com, quic_richardp@quicinc.com, quic_nguyenb@quicinc.com, quic_ziqichen@quicinc.com, bmasney@redhat.com, krzysztof.kozlowski@linaro.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Manivannan Sadhasivam Subject: [PATCH v6 4/5] arm64: dts: qcom: sdm845: Add OPP table support to UFSHC Date: Thu, 12 Oct 2023 11:15:11 +0530 Message-Id: <20231012054512.10963-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231012054512.10963-1-manivannan.sadhasivam@linaro.org> References: <20231012054512.10963-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Krzysztof Kozlowski UFS host controller, when scaling gears, should choose appropriate performance state of RPMh power domain controller along with clock frequency. So let's add the OPP table support to specify both clock frequency and RPMh performance states replacing the old "freq-table-hz" property. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski [mani: Splitted pd change and used rpmhpd_opp_low_svs] Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 42 +++++++++++++++++++++------- 1 file changed, 32 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 055ca80c0075..2ea6eb44953e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2605,22 +2605,44 @@ ufs_mem_hc: ufshc@1d84000 { <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; - freq-table-hz = - <50000000 200000000>, - <0 0>, - <0 0>, - <37500000 150000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>, - <75000000 300000000>; + + operating-points-v2 = <&ufs_opp_table>; interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; interconnect-names = "ufs-ddr", "cpu-ufs"; status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <37500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; ufs_mem_phy: phy@1d87000 {