diff mbox series

[V3,2/4] clk: qcom: branch: Add mem ops support for branch2 clocks

Message ID 20231106103027.3988871-3-quic_imrashai@quicinc.com (mailing list archive)
State Superseded
Headers show
Series Add support for Qualcomm ECPRI clock controller | expand

Commit Message

Imran Shaik Nov. 6, 2023, 10:30 a.m. UTC 
From: Taniya Das <quic_tdas@quicinc.com>

Clock CBCRs with memories need an update for memory before enable/disable
of the clock, which helps retain the respective block's register contents.
Add support for the mem ops to handle this sequence.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
---
 drivers/clk/qcom/clk-branch.c | 39 +++++++++++++++++++++++++++++++++++
 drivers/clk/qcom/clk-branch.h | 21 +++++++++++++++++++
 2 files changed, 60 insertions(+)

Comments

Dmitry Baryshkov Nov. 6, 2023, 1 p.m. UTC | #1 
On Mon, 6 Nov 2023 at 12:31, Imran Shaik <quic_imrashai@quicinc.com> wrote:
>
> From: Taniya Das <quic_tdas@quicinc.com>
>
> Clock CBCRs with memories need an update for memory before enable/disable
> of the clock, which helps retain the respective block's register contents.
> Add support for the mem ops to handle this sequence.
>
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>

It would be nice to have a description of what is 'CBCR with memories'
and how does it differ from CBCR_FORCE_MEM_CORE_ON?

> ---
>  drivers/clk/qcom/clk-branch.c | 39 +++++++++++++++++++++++++++++++++++
>  drivers/clk/qcom/clk-branch.h | 21 +++++++++++++++++++
>  2 files changed, 60 insertions(+)
>
> diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c
> index fc4735f74f0f..61bdd2147bed 100644
> --- a/drivers/clk/qcom/clk-branch.c
> +++ b/drivers/clk/qcom/clk-branch.c
> @@ -1,6 +1,7 @@
>  // SPDX-License-Identifier: GPL-2.0
>  /*
>   * Copyright (c) 2013, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>   */
>
>  #include <linux/kernel.h>
> @@ -134,6 +135,44 @@ static void clk_branch2_disable(struct clk_hw *hw)
>         clk_branch_toggle(hw, false, clk_branch2_check_halt);
>  }
>
> +static int clk_branch2_mem_enable(struct clk_hw *hw)
> +{
> +       struct clk_mem_branch *mem_br = to_clk_mem_branch(hw);
> +       struct clk_branch branch = mem_br->branch;
> +       const char *name = clk_hw_get_name(&branch.clkr.hw);
> +       u32 val;
> +       int ret;
> +
> +       regmap_update_bits(branch.clkr.regmap, mem_br->mem_enable_reg,
> +                       mem_br->mem_enable_ack_mask, mem_br->mem_enable_ack_mask);
> +
> +       ret = regmap_read_poll_timeout(branch.clkr.regmap, mem_br->mem_ack_reg,
> +                       val, val & mem_br->mem_enable_ack_mask, 0, 200);
> +       if (ret) {
> +               WARN(1, "%s mem enable failed\n", name);
> +               return ret;
> +       }
> +
> +       return clk_branch2_enable(hw);
> +}
> +
> +static void clk_branch2_mem_disable(struct clk_hw *hw)
> +{
> +       struct clk_mem_branch *mem_br = to_clk_mem_branch(hw);
> +
> +       regmap_update_bits(mem_br->branch.clkr.regmap, mem_br->mem_enable_reg,
> +                                               mem_br->mem_enable_ack_mask, 0);
> +
> +       return clk_branch2_disable(hw);
> +}
> +
> +const struct clk_ops clk_branch2_mem_ops = {
> +       .enable = clk_branch2_mem_enable,
> +       .disable = clk_branch2_mem_disable,
> +       .is_enabled = clk_is_enabled_regmap,
> +};
> +EXPORT_SYMBOL_GPL(clk_branch2_mem_ops);
> +
>  const struct clk_ops clk_branch2_ops = {
>         .enable = clk_branch2_enable,
>         .disable = clk_branch2_disable,
> diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h
> index 0cf800b9d08d..8ffed603c050 100644
> --- a/drivers/clk/qcom/clk-branch.h
> +++ b/drivers/clk/qcom/clk-branch.h
> @@ -38,6 +38,23 @@ struct clk_branch {
>         struct clk_regmap clkr;
>  };
>
> +/**
> + * struct clk_mem_branch - gating clock which are associated with memories
> + *
> + * @mem_enable_reg: branch clock memory gating register
> + * @mem_ack_reg: branch clock memory ack register
> + * @mem_enable_ack_mask: branch clock memory enable and ack field in @mem_ack_reg
> + * @branch: branch clock gating handle
> + *
> + * Clock which can gate its memories.
> + */
> +struct clk_mem_branch {
> +       u32     mem_enable_reg;
> +       u32     mem_ack_reg;
> +       u32     mem_enable_ack_mask;
> +       struct clk_branch branch;
> +};
> +
>  /* Branch clock common bits for HLOS-owned clocks */
>  #define CBCR_CLK_OFF                   BIT(31)
>  #define CBCR_NOC_FSM_STATUS            GENMASK(30, 28)
> @@ -85,8 +102,12 @@ extern const struct clk_ops clk_branch_ops;
>  extern const struct clk_ops clk_branch2_ops;
>  extern const struct clk_ops clk_branch_simple_ops;
>  extern const struct clk_ops clk_branch2_aon_ops;
> +extern const struct clk_ops clk_branch2_mem_ops;
>
>  #define to_clk_branch(_hw) \
>         container_of(to_clk_regmap(_hw), struct clk_branch, clkr)
>
> +#define to_clk_mem_branch(_hw) \
> +       container_of(to_clk_branch(_hw), struct clk_mem_branch, branch)
> +
>  #endif
> --
> 2.25.1
>
Imran Shaik Nov. 10, 2023, 8:32 a.m. UTC | #2 
On 11/6/2023 6:30 PM, Dmitry Baryshkov wrote:
> On Mon, 6 Nov 2023 at 12:31, Imran Shaik <quic_imrashai@quicinc.com> wrote:
>>
>> From: Taniya Das <quic_tdas@quicinc.com>
>>
>> Clock CBCRs with memories need an update for memory before enable/disable
>> of the clock, which helps retain the respective block's register contents.
>> Add support for the mem ops to handle this sequence.
>>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
> 
> It would be nice to have a description of what is 'CBCR with memories'
> and how does it differ from CBCR_FORCE_MEM_CORE_ON?
> 

This mem_ops implementation is to enable/disable the memories in 
ethernet PHY, prior to turning on the respective clocks. Where as the 
FORCE_MEM_CORE_ON is to keep the memories awake even if the clock is gated.

>> ---
>>   drivers/clk/qcom/clk-branch.c | 39 +++++++++++++++++++++++++++++++++++
>>   drivers/clk/qcom/clk-branch.h | 21 +++++++++++++++++++
>>   2 files changed, 60 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c
>> index fc4735f74f0f..61bdd2147bed 100644
>> --- a/drivers/clk/qcom/clk-branch.c
>> +++ b/drivers/clk/qcom/clk-branch.c
>> @@ -1,6 +1,7 @@
>>   // SPDX-License-Identifier: GPL-2.0
>>   /*
>>    * Copyright (c) 2013, The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>>    */
>>
>>   #include <linux/kernel.h>
>> @@ -134,6 +135,44 @@ static void clk_branch2_disable(struct clk_hw *hw)
>>          clk_branch_toggle(hw, false, clk_branch2_check_halt);
>>   }
>>
>> +static int clk_branch2_mem_enable(struct clk_hw *hw)
>> +{
>> +       struct clk_mem_branch *mem_br = to_clk_mem_branch(hw);
>> +       struct clk_branch branch = mem_br->branch;
>> +       const char *name = clk_hw_get_name(&branch.clkr.hw);
>> +       u32 val;
>> +       int ret;
>> +
>> +       regmap_update_bits(branch.clkr.regmap, mem_br->mem_enable_reg,
>> +                       mem_br->mem_enable_ack_mask, mem_br->mem_enable_ack_mask);
>> +
>> +       ret = regmap_read_poll_timeout(branch.clkr.regmap, mem_br->mem_ack_reg,
>> +                       val, val & mem_br->mem_enable_ack_mask, 0, 200);
>> +       if (ret) {
>> +               WARN(1, "%s mem enable failed\n", name);
>> +               return ret;
>> +       }
>> +
>> +       return clk_branch2_enable(hw);
>> +}
>> +
>> +static void clk_branch2_mem_disable(struct clk_hw *hw)
>> +{
>> +       struct clk_mem_branch *mem_br = to_clk_mem_branch(hw);
>> +
>> +       regmap_update_bits(mem_br->branch.clkr.regmap, mem_br->mem_enable_reg,
>> +                                               mem_br->mem_enable_ack_mask, 0);
>> +
>> +       return clk_branch2_disable(hw);
>> +}
>> +
>> +const struct clk_ops clk_branch2_mem_ops = {
>> +       .enable = clk_branch2_mem_enable,
>> +       .disable = clk_branch2_mem_disable,
>> +       .is_enabled = clk_is_enabled_regmap,
>> +};
>> +EXPORT_SYMBOL_GPL(clk_branch2_mem_ops);
>> +
>>   const struct clk_ops clk_branch2_ops = {
>>          .enable = clk_branch2_enable,
>>          .disable = clk_branch2_disable,
>> diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h
>> index 0cf800b9d08d..8ffed603c050 100644
>> --- a/drivers/clk/qcom/clk-branch.h
>> +++ b/drivers/clk/qcom/clk-branch.h
>> @@ -38,6 +38,23 @@ struct clk_branch {
>>          struct clk_regmap clkr;
>>   };
>>
>> +/**
>> + * struct clk_mem_branch - gating clock which are associated with memories
>> + *
>> + * @mem_enable_reg: branch clock memory gating register
>> + * @mem_ack_reg: branch clock memory ack register
>> + * @mem_enable_ack_mask: branch clock memory enable and ack field in @mem_ack_reg
>> + * @branch: branch clock gating handle
>> + *
>> + * Clock which can gate its memories.
>> + */
>> +struct clk_mem_branch {
>> +       u32     mem_enable_reg;
>> +       u32     mem_ack_reg;
>> +       u32     mem_enable_ack_mask;
>> +       struct clk_branch branch;
>> +};
>> +
>>   /* Branch clock common bits for HLOS-owned clocks */
>>   #define CBCR_CLK_OFF                   BIT(31)
>>   #define CBCR_NOC_FSM_STATUS            GENMASK(30, 28)
>> @@ -85,8 +102,12 @@ extern const struct clk_ops clk_branch_ops;
>>   extern const struct clk_ops clk_branch2_ops;
>>   extern const struct clk_ops clk_branch_simple_ops;
>>   extern const struct clk_ops clk_branch2_aon_ops;
>> +extern const struct clk_ops clk_branch2_mem_ops;
>>
>>   #define to_clk_branch(_hw) \
>>          container_of(to_clk_regmap(_hw), struct clk_branch, clkr)
>>
>> +#define to_clk_mem_branch(_hw) \
>> +       container_of(to_clk_branch(_hw), struct clk_mem_branch, branch)
>> +
>>   #endif
>> --
>> 2.25.1
>>
> 
>
diff mbox series

Patch

diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c
index fc4735f74f0f..61bdd2147bed 100644
--- a/drivers/clk/qcom/clk-branch.c
+++ b/drivers/clk/qcom/clk-branch.c
@@ -1,6 +1,7 @@ 
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/kernel.h>
@@ -134,6 +135,44 @@  static void clk_branch2_disable(struct clk_hw *hw)
 	clk_branch_toggle(hw, false, clk_branch2_check_halt);
 }
 
+static int clk_branch2_mem_enable(struct clk_hw *hw)
+{
+	struct clk_mem_branch *mem_br = to_clk_mem_branch(hw);
+	struct clk_branch branch = mem_br->branch;
+	const char *name = clk_hw_get_name(&branch.clkr.hw);
+	u32 val;
+	int ret;
+
+	regmap_update_bits(branch.clkr.regmap, mem_br->mem_enable_reg,
+			mem_br->mem_enable_ack_mask, mem_br->mem_enable_ack_mask);
+
+	ret = regmap_read_poll_timeout(branch.clkr.regmap, mem_br->mem_ack_reg,
+			val, val & mem_br->mem_enable_ack_mask, 0, 200);
+	if (ret) {
+		WARN(1, "%s mem enable failed\n", name);
+		return ret;
+	}
+
+	return clk_branch2_enable(hw);
+}
+
+static void clk_branch2_mem_disable(struct clk_hw *hw)
+{
+	struct clk_mem_branch *mem_br = to_clk_mem_branch(hw);
+
+	regmap_update_bits(mem_br->branch.clkr.regmap, mem_br->mem_enable_reg,
+						mem_br->mem_enable_ack_mask, 0);
+
+	return clk_branch2_disable(hw);
+}
+
+const struct clk_ops clk_branch2_mem_ops = {
+	.enable = clk_branch2_mem_enable,
+	.disable = clk_branch2_mem_disable,
+	.is_enabled = clk_is_enabled_regmap,
+};
+EXPORT_SYMBOL_GPL(clk_branch2_mem_ops);
+
 const struct clk_ops clk_branch2_ops = {
 	.enable = clk_branch2_enable,
 	.disable = clk_branch2_disable,
diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h
index 0cf800b9d08d..8ffed603c050 100644
--- a/drivers/clk/qcom/clk-branch.h
+++ b/drivers/clk/qcom/clk-branch.h
@@ -38,6 +38,23 @@  struct clk_branch {
 	struct clk_regmap clkr;
 };
 
+/**
+ * struct clk_mem_branch - gating clock which are associated with memories
+ *
+ * @mem_enable_reg: branch clock memory gating register
+ * @mem_ack_reg: branch clock memory ack register
+ * @mem_enable_ack_mask: branch clock memory enable and ack field in @mem_ack_reg
+ * @branch: branch clock gating handle
+ *
+ * Clock which can gate its memories.
+ */
+struct clk_mem_branch {
+	u32	mem_enable_reg;
+	u32	mem_ack_reg;
+	u32	mem_enable_ack_mask;
+	struct clk_branch branch;
+};
+
 /* Branch clock common bits for HLOS-owned clocks */
 #define CBCR_CLK_OFF			BIT(31)
 #define CBCR_NOC_FSM_STATUS		GENMASK(30, 28)
@@ -85,8 +102,12 @@  extern const struct clk_ops clk_branch_ops;
 extern const struct clk_ops clk_branch2_ops;
 extern const struct clk_ops clk_branch_simple_ops;
 extern const struct clk_ops clk_branch2_aon_ops;
+extern const struct clk_ops clk_branch2_mem_ops;
 
 #define to_clk_branch(_hw) \
 	container_of(to_clk_regmap(_hw), struct clk_branch, clkr)
 
+#define to_clk_mem_branch(_hw) \
+	container_of(to_clk_branch(_hw), struct clk_mem_branch, branch)
+
 #endif