From patchwork Mon Nov 20 13:21:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 13461298 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bgdev-pl.20230601.gappssmtp.com header.i=@bgdev-pl.20230601.gappssmtp.com header.b="Ob7A1j+Z" Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 380A4D50 for ; Mon, 20 Nov 2023 05:21:36 -0800 (PST) Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-40839652b97so14263975e9.3 for ; Mon, 20 Nov 2023 05:21:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20230601.gappssmtp.com; s=20230601; t=1700486494; x=1701091294; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Lgka31W3qpZw9qmD0Tl3+W8wAOSMxMGHO0Pnf3Jfow4=; b=Ob7A1j+ZZ5KI3N8qcESLldc7P3G2pt5KxQo+st4aGoaEuAgGdr/SDu1U6JnlLGthnq mKDrO5rty37PoNhF3sbeZ+b03NO407EDv7KQdYoHpfIORWS4YjOcX+XbhJrEoGXT3PtO JgLqhIlReGGHM3XQ/JVoMUp5wOmJGLoJ4O9xwDXfqA/sMWIYCyqo+Dnq/L2R8tOyxPVZ BDiFTVTpcm9cKGwhj4xqFJLaBqf9Slz+2K/XNCfnisN/4BeHUJXaeODeLigVvFyNSH65 /U+ER8ZczGAnTnFHxqbwzuwXcqGcjxbJ3/StHpdiaVIv/bV+p990vash3hWOIzEwlFq7 HO3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700486494; x=1701091294; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lgka31W3qpZw9qmD0Tl3+W8wAOSMxMGHO0Pnf3Jfow4=; b=wyIcG3bxChAm3ZpXJF45S/EWI0OXHq0rcpynanUBGQN+qponSa03A14tSpUt37t/Nw Izzf23x0lZvu86YVDPCSYkZlKbGMsSjY8ORrdBh0fknh9YQEoKzb8T1JtZ/qG/6Hk2q9 oRVtXOMiTFeBHbbRB7MhSuUoXIF3KgfklyZPa+lTpujxk/ZFecOgCmPPKTOraHvDdqEI 4EaDXyyiH+zgJqh83XVXBfZGQ9hq4LiKk7+lEMD4Sm0NbFTas5jYJ9FnnYNpaXOHL2ig i7/19I7YZ83t6/o5hr1OiEEEWGZCnHLOJ+iqLteFVQ4NO+62y1nnQPxGwQ4jC8eqSRKh va1Q== X-Gm-Message-State: AOJu0YzUjFBOZAdxePTnMV1rEy1RAyRFzTSQQVilavG6Qe1qkGLk9DAq ouiJoOB7TF80/3QpyRCOLaAuTA== X-Google-Smtp-Source: AGHT+IFBgB3VsFkfv6Pz5M2syzbfYSZmVRFA5Q7mNG3T8Rq5uhKx7pO4Grzyfci0z8WRHQTbp8PuqA== X-Received: by 2002:a05:600c:1c8b:b0:3fe:f667:4e4c with SMTP id k11-20020a05600c1c8b00b003fef6674e4cmr6416175wms.12.1700486494283; Mon, 20 Nov 2023 05:21:34 -0800 (PST) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:c590:a7ce:883:eba3]) by smtp.gmail.com with ESMTPSA id k18-20020a05600c0b5200b004065e235417sm17329192wmr.21.2023.11.20.05.21.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:21:33 -0800 (PST) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Elliot Berman , Krzysztof Kozlowski , Guru Das Srinagesh , Andrew Halaney , Maximilian Luz , Alex Elder , Srini Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@quicinc.com, Bartosz Golaszewski Subject: [RESEND PATCH v5 10/12] firmware: qcom: tzmem: enable SHM Bridge support Date: Mon, 20 Nov 2023 14:21:16 +0100 Message-Id: <20231120132118.30473-11-brgl@bgdev.pl> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120132118.30473-1-brgl@bgdev.pl> References: <20231120132118.30473-1-brgl@bgdev.pl> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Bartosz Golaszewski Add a new Kconfig option for selecting the SHM Bridge mode of operation for the TrustZone memory allocator. If enabled at build-time, it will still be checked for availability at run-time. If the architecture doesn't support SHM Bridge, the allocator will work just like in the default mode. Signed-off-by: Bartosz Golaszewski Tested-by: Andrew Halaney # sc8280xp-lenovo-thinkpad-x13s --- drivers/firmware/qcom/Kconfig | 10 +++++ drivers/firmware/qcom/qcom_tzmem.c | 65 +++++++++++++++++++++++++++++- 2 files changed, 74 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/qcom/Kconfig b/drivers/firmware/qcom/Kconfig index 237da40de832..e01407e31ae4 100644 --- a/drivers/firmware/qcom/Kconfig +++ b/drivers/firmware/qcom/Kconfig @@ -27,6 +27,16 @@ config QCOM_TZMEM_MODE_DEFAULT Use the default allocator mode. The memory is page-aligned, non-cachable and contiguous. +config QCOM_TZMEM_MODE_SHMBRIDGE + bool "SHM Bridge" + help + Use Qualcomm Shared Memory Bridge. The memory has the same alignment as + in the 'Default' allocator but is also explicitly marked as an SHM Bridge + buffer. + + With this selected, all buffers passed to the TrustZone must be allocated + using the TZMem allocator or else the TrustZone will refuse to use them. + endchoice config QCOM_SCM_DOWNLOAD_MODE_DEFAULT diff --git a/drivers/firmware/qcom/qcom_tzmem.c b/drivers/firmware/qcom/qcom_tzmem.c index 68ca59c5598e..8010af80fd59 100644 --- a/drivers/firmware/qcom/qcom_tzmem.c +++ b/drivers/firmware/qcom/qcom_tzmem.c @@ -55,7 +55,70 @@ static void qcom_tzmem_cleanup_pool(struct qcom_tzmem_pool *pool) } -#endif /* CONFIG_QCOM_TZMEM_MODE_DEFAULT */ +#elif IS_ENABLED(CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE) + +#include + +#define QCOM_SHM_BRIDGE_NUM_VM_SHIFT 9 + +static bool qcom_tzmem_using_shm_bridge; + +static int qcom_tzmem_init(void) +{ + int ret; + + ret = qcom_scm_shm_bridge_enable(); + if (ret == -EOPNOTSUPP) { + dev_info(qcom_tzmem_dev, "SHM Bridge not supported\n"); + return 0; + } + + if (!ret) + qcom_tzmem_using_shm_bridge = true; + + return ret; +} + +static int qcom_tzmem_init_pool(struct qcom_tzmem_pool *pool) +{ + u64 pfn_and_ns_perm, ipfn_and_s_perm, size_and_flags, ns_perms; + int ret; + + if (!qcom_tzmem_using_shm_bridge) + return 0; + + ns_perms = (QCOM_SCM_PERM_WRITE | QCOM_SCM_PERM_READ); + pfn_and_ns_perm = (u64)pool->pbase | ns_perms; + ipfn_and_s_perm = (u64)pool->pbase | ns_perms; + size_and_flags = pool->size | (1 << QCOM_SHM_BRIDGE_NUM_VM_SHIFT); + + u64 *handle __free(kfree) = kzalloc(sizeof(*handle), GFP_KERNEL); + if (!handle) + return -ENOMEM; + + ret = qcom_scm_shm_bridge_create(qcom_tzmem_dev, pfn_and_ns_perm, + ipfn_and_s_perm, size_and_flags, + QCOM_SCM_VMID_HLOS, handle); + if (ret) + return ret; + + pool->priv = no_free_ptr(handle); + + return 0; +} + +static void qcom_tzmem_cleanup_pool(struct qcom_tzmem_pool *pool) +{ + u64 *handle = pool->priv; + + if (!qcom_tzmem_using_shm_bridge) + return; + + qcom_scm_shm_bridge_delete(qcom_tzmem_dev, *handle); + kfree(handle); +} + +#endif /* CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE */ /** * qcom_tzmem_pool_new() - Create a new TZ memory pool.