From patchwork Tue Nov 28 19:57:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 13471646 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="k7jvF2/U" Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBC4619AB; Tue, 28 Nov 2023 12:04:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701201851; x=1732737851; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DJwJ2feXkZ/U/Pmfh4iLbq3pwB7LIbDdlMhBN+ByETk=; b=k7jvF2/URP0DOdzqCx259j5l//hUAZamT6JHXl5ULOu7VqxJI/uPcuNT UnVdSTmol7Ead+C+6wVgLrU09X8xxDfg/prAB+0SAivMGUXzn0+cZC7PV hJF4aPQbcke59tGYulJX2VDr4eeMNM6VdWFgYT5Jg5XY9XBQTINoY9TcR jBWixhZRDqTo8shjAIwa8NNcR3LFBW7MAIHFQMZGiL4s5UoRzi2FOzqms 9sRbe3arbOzm3MkNPIWx+VXSH/IQ6p5i4SzP0IEhmmH/ccfpbslkKD92J 3JxqDcKi8dheeXtTxXl6/hVJuO2EPhVo8RfplfvTdiaNEmQgNnj37sHNm g==; X-IronPort-AV: E=McAfee;i="6600,9927,10908"; a="457345630" X-IronPort-AV: E=Sophos;i="6.04,234,1695711600"; d="scan'208";a="457345630" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2023 12:02:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10908"; a="772420466" X-IronPort-AV: E=Sophos;i="6.04,234,1695711600"; d="scan'208";a="772420466" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga007.fm.intel.com with ESMTP; 28 Nov 2023 12:02:28 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id C1A85B66; Tue, 28 Nov 2023 22:01:58 +0200 (EET) From: Andy Shevchenko To: Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Rasmus Villemoes , =?utf-8?q?Jonathan_Neusch?= =?utf-8?q?=C3=A4fer?= , Krzysztof Kozlowski , =?utf-8?q?Uwe_Kleine-?= =?utf-8?q?K=C3=B6nig?= , Geert Uytterhoeven , Biju Das , Claudiu Beznea , Jianlong Huang , linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, openbmc@lists.ozlabs.org, linux-mips@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org Cc: Ray Jui , Scott Branden , Broadcom internal kernel review list , Dong Aisheng , Fabio Estevam , Shawn Guo , Jacky Bai , Pengutronix Kernel Team , Sascha Hauer , NXP Linux Team , Sean Wang , Paul Cercueil , Lakshmi Sowjanya D , Andy Gross , Bjorn Andersson , Konrad Dybcio , Emil Renner Berthing , Hal Feng Subject: [PATCH v3 17/22] pinctrl: ingenic: Convert to use grp member Date: Tue, 28 Nov 2023 21:57:06 +0200 Message-ID: <20231128200155.438722-18-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1.gbec44491f096 In-Reply-To: <20231128200155.438722-1-andriy.shevchenko@linux.intel.com> References: <20231128200155.438722-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Convert drivers to use grp member embedded in struct group_desc. Acked-by: Paul Cercueil Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-ingenic.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 393873de910a..6806fede5df4 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -3756,17 +3756,17 @@ static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev, return -EINVAL; dev_dbg(pctldev->dev, "enable function %s group %s\n", - func->name, grp->name); + func->name, grp->grp.name); mode = (uintptr_t)grp->data; if (mode <= 3) { - for (i = 0; i < grp->num_pins; i++) - ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], mode); + for (i = 0; i < grp->grp.npins; i++) + ingenic_pinmux_set_pin_fn(jzpc, grp->grp.pins[i], mode); } else { pin_modes = grp->data; - for (i = 0; i < grp->num_pins; i++) - ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]); + for (i = 0; i < grp->grp.npins; i++) + ingenic_pinmux_set_pin_fn(jzpc, grp->grp.pins[i], pin_modes[i]); } return 0; @@ -4293,12 +4293,12 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) for (i = 0; i < chip_info->num_groups; i++) { const struct group_desc *group = &chip_info->groups[i]; + const struct pingroup *grp = &group->grp; - err = pinctrl_generic_add_group(jzpc->pctl, group->name, - group->pins, group->num_pins, group->data); + err = pinctrl_generic_add_group(jzpc->pctl, grp->name, grp->pins, grp->npins, + group->data); if (err < 0) { - dev_err(dev, "Failed to register group %s\n", - group->name); + dev_err(dev, "Failed to register group %s\n", grp->name); return err; } }