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[93.34.89.13]) by smtp.googlemail.com with ESMTPSA id b19-20020a05600c4e1300b0040648217f4fsm321406wmq.39.2023.11.28.18.12.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 18:12:37 -0800 (PST) From: Christian Marangi To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andy Gross , Bjorn Andersson , Konrad Dybcio , linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Christian Marangi Subject: [net-next PATCH 09/14] net: phy: at803x: remove specific qca808x check from at803x functions Date: Wed, 29 Nov 2023 03:12:14 +0100 Message-Id: <20231129021219.20914-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231129021219.20914-1-ansuelsmth@gmail.com> References: <20231129021219.20914-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Remove specific qca808x check from at803x generic functions. While this cause a bit of code duplication, this is needed in preparation for splitting the driver per PHY family and detaching qca808x specific bits from the at803x driver. Signed-off-by: Christian Marangi --- drivers/net/phy/at803x.c | 107 ++++++++++++++++++++++++++------------- 1 file changed, 71 insertions(+), 36 deletions(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 8f5878ccb1a8..475b96165f45 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -1043,24 +1043,6 @@ static int at803x_config_aneg(struct phy_device *phydev) */ ret = 0; - if (phydev->drv->phy_id == QCA8081_PHY_ID) { - int phy_ctrl = 0; - - /* The reg MII_BMCR also needs to be configured for force mode, the - * genphy_config_aneg is also needed. - */ - if (phydev->autoneg == AUTONEG_DISABLE) - genphy_c45_pma_setup_forced(phydev); - - if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising)) - phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G; - - ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, - MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl); - if (ret < 0) - return ret; - } - return __genphy_config_aneg(phydev, ret); } @@ -1197,14 +1179,8 @@ static int at803x_cdt_start(struct phy_device *phydev, int pair) { u16 cdt; - /* qca8081 takes the different bit 15 to enable CDT test */ - if (phydev->drv->phy_id == QCA8081_PHY_ID) - cdt = QCA808X_CDT_ENABLE_TEST | - QCA808X_CDT_LENGTH_UNIT | - QCA808X_CDT_INTER_CHECK_DIS; - else - cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | - AT803X_CDT_ENABLE_TEST; + cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | + AT803X_CDT_ENABLE_TEST; return phy_write(phydev, AT803X_CDT, cdt); } @@ -1212,16 +1188,10 @@ static int at803x_cdt_start(struct phy_device *phydev, int pair) static int at803x_cdt_wait_for_completion(struct phy_device *phydev) { int val, ret; - u16 cdt_en; - - if (phydev->drv->phy_id == QCA8081_PHY_ID) - cdt_en = QCA808X_CDT_ENABLE_TEST; - else - cdt_en = AT803X_CDT_ENABLE_TEST; /* One test run takes about 25ms */ ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, - !(val & cdt_en), + !(val & AT803X_CDT_ENABLE_TEST), 30000, 100000, true); return ret < 0 ? ret : 0; @@ -1845,6 +1815,47 @@ static int qca8327_suspend(struct phy_device *phydev) return qca83xx_suspend(phydev); } +static int qca808x_config_aneg(struct phy_device *phydev) +{ + int phy_ctrl = 0; + int ret; + + ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); + if (ret < 0) + return ret; + + /* Changes of the midx bits are disruptive to the normal operation; + * therefore any changes to these registers must be followed by a + * software reset to take effect. + */ + if (ret == 1) { + ret = genphy_soft_reset(phydev); + if (ret < 0) + return ret; + } + + /* Do not restart auto-negotiation by setting ret to 0 defautly, + * when calling __genphy_config_aneg later. + */ + ret = 0; + + /* The reg MII_BMCR also needs to be configured for force mode, the + * genphy_config_aneg is also needed. + */ + if (phydev->autoneg == AUTONEG_DISABLE) + genphy_c45_pma_setup_forced(phydev); + + if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising)) + phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G; + + ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, + MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl); + if (ret < 0) + return ret; + + return __genphy_config_aneg(phydev, ret); +} + static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) { int ret; @@ -2104,6 +2115,30 @@ static int qca808x_cable_test_start(struct phy_device *phydev) return 0; } +static int qca808x_cdt_start(struct phy_device *phydev) +{ + u16 cdt; + + /* qca8081 takes the different bit 15 to enable CDT test */ + cdt = QCA808X_CDT_ENABLE_TEST | + QCA808X_CDT_LENGTH_UNIT | + QCA808X_CDT_INTER_CHECK_DIS; + + return phy_write(phydev, AT803X_CDT, cdt); +} + +static int qca808x_cdt_wait_for_completition(struct phy_device *phydev) +{ + int val, ret; + + /* One test run takes about 25ms */ + ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, + !(val & QCA808X_CDT_ENABLE_TEST), + 30000, 100000, true); + + return ret < 0 ? ret : 0; +} + static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished) { int ret, val; @@ -2111,11 +2146,11 @@ static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finish *finished = false; - ret = at803x_cdt_start(phydev, 0); + ret = qca808x_cdt_start(phydev); if (ret) return ret; - ret = at803x_cdt_wait_for_completion(phydev); + ret = qca808x_cdt_wait_for_completition(phydev); if (ret) return ret; @@ -2360,7 +2395,7 @@ static struct phy_driver at803x_driver[] = { .set_wol = at803x_set_wol, .get_wol = at803x_get_wol, .get_features = qca808x_get_features, - .config_aneg = at803x_config_aneg, + .config_aneg = qca808x_config_aneg, .suspend = genphy_suspend, .resume = genphy_resume, .read_status = qca808x_read_status,