From patchwork Tue Dec 5 06:24:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 13479423 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="HLAYc72O" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B19C189; Mon, 4 Dec 2023 22:25:24 -0800 (PST) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3B55JB9i018375; Tue, 5 Dec 2023 06:25:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=Euqp5P+IB5DfGLBBXIW9O2xkcCpZXSRz38F5YbDgNGE=; b=HLAYc72OSS/D4TYugt+NwrUV2WrNlwgBouUSaKlCsCwnyzTb3UR00FwV9YI5xn8RPzkl cq6nJsSzQ4bPXz4gcoWYNWkbnptunyOEc/IYKZYnKuigtcC9sN+RhNCv6dYzBjXwKOr2 7SwD7y7TNrzOxcfyuH0pdDSrN79GMlwKWWwc70ukj/BKkQa4po7NDHNgvwPnPjYaVu1h sgtt+tLLe1YQ9IprTLTqgdv5JdzuA/z6s48s4TNwzuCkV53ddOiMBpUquY82Or/muAKb uUL+zyOoznUn+WzVmz87Hs+5NpCbWNZYzTcCtw5SIoerCp8z94kTPyAGLnavay/aZfs2 oQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3usfu79xvj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 05 Dec 2023 06:25:05 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3B56P4Ui023119 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 5 Dec 2023 06:25:04 GMT Received: from blr-ubuntu-253.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 4 Dec 2023 22:24:57 -0800 From: Sibi Sankar To: , , , , , CC: , , , , , , , , , , , , , , , , , , Sibi Sankar Subject: [PATCH V5 5/5] arm64: defconfig: Enable X1E80100 SoC base configs Date: Tue, 5 Dec 2023 11:54:03 +0530 Message-ID: <20231205062403.14848-6-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231205062403.14848-1-quic_sibis@quicinc.com> References: <20231205062403.14848-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: wQg3jiGT6ZuMWQwDz8fISdw6hhGdcX_g X-Proofpoint-ORIG-GUID: wQg3jiGT6ZuMWQwDz8fISdw6hhGdcX_g X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-05_03,2023-12-04_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 adultscore=0 clxscore=1015 malwarescore=0 bulkscore=0 impostorscore=0 mlxlogscore=856 priorityscore=1501 mlxscore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2312050052 From: Rajendra Nayak Enable GCC, Pinctrl and Interconnect configs for Qualcomm's X1E80100 SoC which is required to boot X1E80100 QCP/CRD boards to a console shell. The configs are required to be marked as builtin and not modules due to the console driver dependencies. Signed-off-by: Rajendra Nayak Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Reviewed-by: Krzysztof Kozlowski --- v5: * Rename gcc config to CLK_X1E80100_GCC [Krzysztof/Abel/Bryan]. arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 3e7832c64708..ffaa9f9fa10f 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -616,6 +616,7 @@ CONFIG_PINCTRL_SM8450_LPASS_LPI=m CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m CONFIG_PINCTRL_SM8550=y CONFIG_PINCTRL_SM8550_LPASS_LPI=m +CONFIG_PINCTRL_X1E80100=y CONFIG_PINCTRL_LPASS_LPI=m CONFIG_GPIO_AGGREGATOR=m CONFIG_GPIO_ALTERA=m @@ -1220,6 +1221,7 @@ CONFIG_COMMON_CLK_MT8192_SCP_ADSP=y CONFIG_COMMON_CLK_MT8192_VDECSYS=y CONFIG_COMMON_CLK_MT8192_VENCSYS=y CONFIG_COMMON_CLK_QCOM=y +CONFIG_CLK_X1E80100_GCC=y CONFIG_QCOM_A53PLL=y CONFIG_QCOM_CLK_APCS_MSM8916=y CONFIG_QCOM_CLK_APCC_MSM8996=y @@ -1528,6 +1530,7 @@ CONFIG_INTERCONNECT_QCOM_SM8250=m CONFIG_INTERCONNECT_QCOM_SM8350=m CONFIG_INTERCONNECT_QCOM_SM8450=y CONFIG_INTERCONNECT_QCOM_SM8550=y +CONFIG_INTERCONNECT_QCOM_X1E80100=y CONFIG_COUNTER=m CONFIG_RZ_MTU3_CNT=m CONFIG_HTE=y