| Message ID | 20231208050641.32582-12-quic_abhinavk@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | [v2,01/16] drm/msm/dpu: add formats check for writeback encoder | expand |
On Fri, 8 Dec 2023 at 07:07, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote: > > In preparation of setting up CDM block, add the logic to disable it > properly during encoder cleanup. > > changes in v2: > - call update_pending_flush_cdm even when bind_pingpong_blk > is not present > > Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 ++++++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 ++ > 2 files changed, 12 insertions(+) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Minor nit below > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > index aa1a1646b322..862912727925 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > @@ -26,6 +26,7 @@ > #include "dpu_hw_dspp.h" > #include "dpu_hw_dsc.h" > #include "dpu_hw_merge3d.h" > +#include "dpu_hw_cdm.h" > #include "dpu_formats.h" > #include "dpu_encoder_phys.h" > #include "dpu_crtc.h" > @@ -2050,6 +2051,15 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) > phys_enc->hw_pp->merge_3d->idx); > } > > + if (phys_enc->hw_cdm) { > + if (phys_enc->hw_cdm->ops.bind_pingpong_blk && phys_enc->hw_pp) > + phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm, > + false, phys_enc->hw_pp->idx); PINGPONG_NONE > + if (phys_enc->hw_ctl->ops.update_pending_flush_cdm) > + phys_enc->hw_ctl->ops.update_pending_flush_cdm(phys_enc->hw_ctl, > + phys_enc->hw_cdm->idx); > + } > + > if (dpu_enc->dsc) { > dpu_encoder_unprep_dsc(dpu_enc); > dpu_enc->dsc = NULL; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > index b6b48e2c63ef..410f6225789c 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > @@ -151,6 +151,7 @@ enum dpu_intr_idx { > * @hw_pp: Hardware interface to the ping pong registers > * @hw_intf: Hardware interface to the intf registers > * @hw_wb: Hardware interface to the wb registers > + * @hw_cdm: Hardware interface to the CDM registers > * @dpu_kms: Pointer to the dpu_kms top level > * @cached_mode: DRM mode cached at mode_set time, acted on in enable > * @enabled: Whether the encoder has enabled and running a mode > @@ -179,6 +180,7 @@ struct dpu_encoder_phys { > struct dpu_hw_pingpong *hw_pp; > struct dpu_hw_intf *hw_intf; > struct dpu_hw_wb *hw_wb; > + struct dpu_hw_cdm *hw_cdm; > struct dpu_kms *dpu_kms; > struct drm_display_mode cached_mode; > enum dpu_enc_split_role split_role; > -- > 2.40.1 >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index aa1a1646b322..862912727925 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -26,6 +26,7 @@ #include "dpu_hw_dspp.h" #include "dpu_hw_dsc.h" #include "dpu_hw_merge3d.h" +#include "dpu_hw_cdm.h" #include "dpu_formats.h" #include "dpu_encoder_phys.h" #include "dpu_crtc.h" @@ -2050,6 +2051,15 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) phys_enc->hw_pp->merge_3d->idx); } + if (phys_enc->hw_cdm) { + if (phys_enc->hw_cdm->ops.bind_pingpong_blk && phys_enc->hw_pp) + phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm, + false, phys_enc->hw_pp->idx); + if (phys_enc->hw_ctl->ops.update_pending_flush_cdm) + phys_enc->hw_ctl->ops.update_pending_flush_cdm(phys_enc->hw_ctl, + phys_enc->hw_cdm->idx); + } + if (dpu_enc->dsc) { dpu_encoder_unprep_dsc(dpu_enc); dpu_enc->dsc = NULL; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index b6b48e2c63ef..410f6225789c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -151,6 +151,7 @@ enum dpu_intr_idx { * @hw_pp: Hardware interface to the ping pong registers * @hw_intf: Hardware interface to the intf registers * @hw_wb: Hardware interface to the wb registers + * @hw_cdm: Hardware interface to the CDM registers * @dpu_kms: Pointer to the dpu_kms top level * @cached_mode: DRM mode cached at mode_set time, acted on in enable * @enabled: Whether the encoder has enabled and running a mode @@ -179,6 +180,7 @@ struct dpu_encoder_phys { struct dpu_hw_pingpong *hw_pp; struct dpu_hw_intf *hw_intf; struct dpu_hw_wb *hw_wb; + struct dpu_hw_cdm *hw_cdm; struct dpu_kms *dpu_kms; struct drm_display_mode cached_mode; enum dpu_enc_split_role split_role;
In preparation of setting up CDM block, add the logic to disable it properly during encoder cleanup. changes in v2: - call update_pending_flush_cdm even when bind_pingpong_blk is not present Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 ++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 ++ 2 files changed, 12 insertions(+)