@@ -35,15 +35,36 @@
/* MDIO clock source frequency is fixed to 100M */
#define IPQ_MDIO_CLK_RATE 100000000
+/* SoC UNIPHY fixed clock */
+#define IPQ_UNIPHY_AHB_CLK_RATE 100000000
+#define IPQ_UNIPHY_SYS_CLK_RATE 24000000
+
#define IPQ_PHY_SET_DELAY_US 100000
/* Maximum SOC PCS(uniphy) number on IPQ platform */
#define ETH_LDO_RDY_CNT 3
+enum mdio_clk_id {
+ MDIO_CLK_MDIO_AHB,
+ MDIO_CLK_UNIPHY0_AHB,
+ MDIO_CLK_UNIPHY0_SYS,
+ MDIO_CLK_UNIPHY1_AHB,
+ MDIO_CLK_UNIPHY1_SYS,
+ MDIO_CLK_CNT
+};
+
struct ipq4019_mdio_data {
void __iomem *membase;
void __iomem *eth_ldo_rdy[ETH_LDO_RDY_CNT];
- struct clk *mdio_clk;
+ struct clk *clk[MDIO_CLK_CNT];
+};
+
+static const char *const mdio_clk_name[] = {
+ "gcc_mdio_ahb_clk",
+ "uniphy0_ahb",
+ "uniphy0_sys",
+ "uniphy1_ahb",
+ "uniphy1_sys"
};
static int ipq4019_mdio_wait_busy(struct mii_bus *bus)
@@ -209,14 +230,43 @@ static int ipq4019_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum,
static int ipq_mdio_reset(struct mii_bus *bus)
{
struct ipq4019_mdio_data *priv = bus->priv;
- int ret;
+ unsigned long rate;
+ int ret, index;
- /* Configure MDIO clock source frequency if clock is specified in the device tree */
- ret = clk_set_rate(priv->mdio_clk, IPQ_MDIO_CLK_RATE);
- if (ret)
- return ret;
+ /* For the platform ipq5332, there are two SoC uniphies available
+ * for connecting with ethernet PHY, the SoC uniphy gcc clock
+ * should be enabled for resetting the connected device such
+ * as qca8386 switch, qca8081 PHY or other PHYs effectively.
+ *
+ * Configure MDIO/UNIPHY clock source frequency if clock instance
+ * is specified in the device tree.
+ */
+ for (index = MDIO_CLK_MDIO_AHB; index < MDIO_CLK_CNT; index++) {
+ switch (index) {
+ case MDIO_CLK_MDIO_AHB:
+ rate = IPQ_MDIO_CLK_RATE;
+ break;
+ case MDIO_CLK_UNIPHY0_AHB:
+ case MDIO_CLK_UNIPHY1_AHB:
+ rate = IPQ_UNIPHY_AHB_CLK_RATE;
+ break;
+ case MDIO_CLK_UNIPHY0_SYS:
+ case MDIO_CLK_UNIPHY1_SYS:
+ rate = IPQ_UNIPHY_SYS_CLK_RATE;
+ break;
+ default:
+ break;
+ }
+
+ ret = clk_set_rate(priv->clk[index], rate);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(priv->clk[index]);
+ if (ret)
+ return ret;
+ }
- ret = clk_prepare_enable(priv->mdio_clk);
if (ret == 0)
mdelay(10);
@@ -240,10 +290,6 @@ static int ipq4019_mdio_probe(struct platform_device *pdev)
if (IS_ERR(priv->membase))
return PTR_ERR(priv->membase);
- priv->mdio_clk = devm_clk_get_optional(&pdev->dev, "gcc_mdio_ahb_clk");
- if (IS_ERR(priv->mdio_clk))
- return PTR_ERR(priv->mdio_clk);
-
/* These platform resources are provided on the chipset IPQ5018 or
* IPQ5332.
*/
@@ -271,6 +317,13 @@ static int ipq4019_mdio_probe(struct platform_device *pdev)
}
}
+ for (index = 0; index < MDIO_CLK_CNT; index++) {
+ priv->clk[index] = devm_clk_get_optional(&pdev->dev,
+ mdio_clk_name[index]);
+ if (IS_ERR(priv->clk[index]))
+ return PTR_ERR(priv->clk[index]);
+ }
+
bus->name = "ipq4019_mdio";
bus->read = ipq4019_mdio_read_c22;
bus->write = ipq4019_mdio_write_c22;
On the platform ipq5332, the related SoC uniphy GCC clocks need to be enabled for making the MDIO slave devices accessible. These UNIPHY clocks are from the SoC platform GCC clock provider, which are enabled for the connected PHY devices working. Signed-off-by: Luo Jie <quic_luoj@quicinc.com> --- drivers/net/mdio/mdio-ipq4019.c | 75 ++++++++++++++++++++++++++++----- 1 file changed, 64 insertions(+), 11 deletions(-)