From patchwork Thu Dec 14 09:10:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13492616 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="zt4ogbpH" Received: from mail-qk1-x729.google.com (mail-qk1-x729.google.com [IPv6:2607:f8b0:4864:20::729]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45F1410F for ; Thu, 14 Dec 2023 01:11:42 -0800 (PST) Received: by mail-qk1-x729.google.com with SMTP id af79cd13be357-77f37d19b6fso423820785a.2 for ; Thu, 14 Dec 2023 01:11:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702545101; x=1703149901; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1DxFXPJYgIG7bY+rEjLLq6eWKt7yGgrHuHLxSAUgD04=; b=zt4ogbpHMlAx7+8/W/PMq+CJyvCc+yE4SCshQ48Le7NvVvz7qlUaGLfcOJp6W8JqxO Qv7neudkMyrioY7I4Ga9PkHS72NNUY1bVXca/T981wFIc6JQ7Xr/grUiM20Hiry4pn1k hlFuXKZ9Ta5hAawRCdruh/KvuqYdrVnx5YmgE10dimPYBo9lRsFqEYxMPyz5YUXYlRoK gG7ienbyF/xhbxi6BeuzWbaclcQkarYYXdRNb8w+N8ZqjfFhEcgrzfR324b34dPR3o6t toZi+Lgv7ZIh0zFTPzt0/exasSlpA7cKcKRG7yH+krhyL2Y9iXqj711r7oFa++ado7Gn cWrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702545101; x=1703149901; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1DxFXPJYgIG7bY+rEjLLq6eWKt7yGgrHuHLxSAUgD04=; b=ha/fGNberswmhR7fpFx1fZeantuSH02N7ZoAMuCNW3oE8mAgeddoRMj/7ixocxxKtA 4Uz4HBwxVlKL8Nfh6caTaVs/2PgbqyVY05/KfJEuXiFbTyYB+8+jx60u+qiHqfka8/1m y0SWaUm8v0KuaooGnWVNkuERXcyimQAEVHU8sAtTiSLfk5V0N8eDlZ+FS3FI6Ym6nBqC y7bBWEebLU9zgELVIx3kWd19MNKUz8RQhG/Mx4mD0MHXx4YbnvkmV+JE6zJ19xvcwNDR hSotLBaTSHOujBOGYJLreWlRzSAVBN1Ir7WuKw32bDW08Zlnx2ED2tILIvXPToC2tUsG 3wyA== X-Gm-Message-State: AOJu0YzpE1MCfXknEWS/kxOIRks+WefEF2S1n8qLtdwlFWjLaLvFLqGI uk12ZAb24CIbO89KiIKxvWvc X-Google-Smtp-Source: AGHT+IFGeYRRHFMd5RKI2JUYh2LUqufJuMqCc51bmtyQWkYRShHZtBSfcVSJiI4Tsb3u+TyDOkV2ug== X-Received: by 2002:a05:620a:cef:b0:77e:fba3:4f0e with SMTP id c15-20020a05620a0cef00b0077efba34f0emr9799895qkj.100.1702545101407; Thu, 14 Dec 2023 01:11:41 -0800 (PST) Received: from localhost.localdomain ([117.213.102.12]) by smtp.gmail.com with ESMTPSA id qt13-20020a05620a8a0d00b0077d75164ef9sm5144119qkn.124.2023.12.14.01.11.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 01:11:41 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, konrad.dybcio@linaro.org, vkoul@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 04/16] clk: qcom: gcc-sc8180x: Add missing UFS QREF clocks Date: Thu, 14 Dec 2023 14:40:49 +0530 Message-Id: <20231214091101.45713-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231214091101.45713-1-manivannan.sadhasivam@linaro.org> References: <20231214091101.45713-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add missing QREF clocks for UFS MEM and UFS CARD controllers. Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x") Signed-off-by: Manivannan Sadhasivam --- drivers/clk/qcom/gcc-sc8180x.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c index ae2147381559..544567db45f1 100644 --- a/drivers/clk/qcom/gcc-sc8180x.c +++ b/drivers/clk/qcom/gcc-sc8180x.c @@ -3347,6 +3347,19 @@ static struct clk_branch gcc_ufs_card_2_unipro_core_clk = { }, }; +static struct clk_branch gcc_ufs_card_clkref_en = { + .halt_reg = 0x8c004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8c004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_ufs_card_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_ufs_card_ahb_clk = { .halt_reg = 0x75014, .halt_check = BRANCH_HALT, @@ -3561,6 +3574,19 @@ static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = { }, }; +static struct clk_branch gcc_ufs_mem_clkref_en = { + .halt_reg = 0x8c000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8c000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_ufs_mem_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_ufs_phy_ahb_clk = { .halt_reg = 0x77014, .halt_check = BRANCH_HALT, @@ -4413,6 +4439,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = { [GCC_UFS_CARD_2_TX_SYMBOL_0_CLK] = &gcc_ufs_card_2_tx_symbol_0_clk.clkr, [GCC_UFS_CARD_2_UNIPRO_CORE_CLK] = &gcc_ufs_card_2_unipro_core_clk.clkr, [GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_2_unipro_core_clk_src.clkr, + [GCC_UFS_CARD_CLKREF_EN] = &gcc_ufs_card_clkref_en.clkr, [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, @@ -4429,6 +4456,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = { [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr, [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr, + [GCC_UFS_MEM_CLKREF_EN] = &gcc_ufs_mem_clkref_en.clkr, [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,