From patchwork Wed Dec 20 13:38:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibek Kumar Patro X-Patchwork-Id: 13500092 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24503364B5; Wed, 20 Dec 2023 13:39:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ecRH62d2" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BKCgseG020111; Wed, 20 Dec 2023 13:38:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=qcppdkim1; bh=tek7c6ok5/bkwR1YBLY8 2Ui6xRBpZx3XrXJqnyPIgS8=; b=ecRH62d2EMyCYZvzQ7ZfGse5tUBoI+CDmSvz gR9jIHiMsJfTeWdpLXQCkXKx7QziQqv9D8Ug83LGISa3FrU+08Vd68IxpsQPNla7 41e8qlEkq2UfQ8ucoBLIms24cR8oMlEvxN6CLskfidXUsk+NSAnq83vGcTGyW9NW 9weIhsFWhzC/2FUHOlRlLr5KgoYJwrCQgQikTzhPCa4hW0F+xxVBMkIGIgdHtPOq +uuUSy+BbRdJDLmbvh1X0/SjJZH2g8xm2pxI4ypgiCTgvIq1hcQXxmlJfareJ2ir 8hx0kF5FNG7ED/eHITohGHn8N6cjxVek08ZYtCVufv3/gKKQvQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3v3xhngduq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 13:38:55 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BKDcsYU003060 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 13:38:54 GMT Received: from hu-bibekkum-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 20 Dec 2023 05:38:48 -0800 From: Bibek Kumar Patro To: , , , , , , , , , , , , , , CC: , , , , , Bibek Kumar Patro Subject: [PATCH v6 3/5] iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings Date: Wed, 20 Dec 2023 19:08:06 +0530 Message-ID: <20231220133808.5654-4-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231220133808.5654-1-quic_bibekkum@quicinc.com> References: <20231220133808.5654-1-quic_bibekkum@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: hyFzIabU0wLVa5q2aBdAcu3BPyZAVYoh X-Proofpoint-GUID: hyFzIabU0wLVa5q2aBdAcu3BPyZAVYoh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 adultscore=0 bulkscore=0 mlxscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 suspectscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312200097 Currently in Qualcomm SoCs the default prefetch is set to 1 which allows the TLB to fetch just the next page table. MMU-500 features ACTLR register which is implementation defined and is used for Qualcomm SoCs to have a custom prefetch setting enabling TLB to prefetch the next set of page tables accordingly allowing for faster translations. ACTLR value is unique for each SMR (Stream matching register) and stored in a pre-populated table. This value is set to the register during context bank initialisation. Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 45 ++++++++++++++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 6 ++- drivers/iommu/arm/arm-smmu/arm-smmu.c | 5 ++- drivers/iommu/arm/arm-smmu/arm-smmu.h | 5 +++ 4 files changed, 58 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 20c9836d859b..1cefdd0ca110 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -24,6 +24,12 @@ #define CPRE (1 << 1) #define CMTLB (1 << 0) +struct actlr_config { + u16 sid; + u16 mask; + u32 actlr; +}; + static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) { return container_of(smmu, struct qcom_smmu, smmu); @@ -215,9 +221,38 @@ static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu) return true; } +static void qcom_smmu_set_actlr(struct device *dev, struct arm_smmu_device *smmu, int cbndx, + const struct actlr_config *actlrcfg) +{ + struct arm_smmu_master_cfg *cfg = dev_iommu_priv_get(dev); + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct arm_smmu_smr *smr; + u16 mask; + int idx; + u16 id; + int i; + + for (; actlrcfg->sid || actlrcfg->mask || actlrcfg->actlr; actlrcfg++) { + id = actlrcfg->sid; + mask = actlrcfg->mask; + + for_each_cfg_sme(cfg, fwspec, i, idx) { + smr = &smmu->smrs[idx]; + if (smr_is_subset(smr, id, mask)) { + arm_smmu_cb_write(smmu, cbndx, ARM_SMMU_CB_ACTLR, + actlrcfg->actlr); + break; + } + } + } +} + static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) { + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); + int cbndx = smmu_domain->cfg.cbndx; struct adreno_smmu_priv *priv; smmu_domain->cfg.flush_walk_prefer_tlbiasid = true; @@ -248,6 +283,9 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, priv->set_stall = qcom_adreno_smmu_set_stall; priv->resume_translation = qcom_adreno_smmu_resume_translation; + if (qsmmu->data->actlrcfg_gfx) + qcom_smmu_set_actlr(dev, smmu, cbndx, qsmmu->data->actlrcfg_gfx); + return 0; } @@ -274,6 +312,13 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain, struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) { + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); + int cbndx = smmu_domain->cfg.cbndx; + + if (qsmmu->data->actlrcfg) + qcom_smmu_set_actlr(dev, smmu, cbndx, qsmmu->data->actlrcfg); + smmu_domain->cfg.flush_walk_prefer_tlbiasid = true; return 0; diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h index f3b91963e234..cb4cb402c202 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _ARM_SMMU_QCOM_H @@ -24,7 +24,11 @@ struct qcom_smmu_config { const u32 *reg_offset; }; +struct actlr_config; + struct qcom_smmu_match_data { + const struct actlr_config *actlrcfg; + const struct actlr_config *actlrcfg_gfx; const struct qcom_smmu_config *cfg; const struct arm_smmu_impl *impl; const struct arm_smmu_impl *adreno_impl; diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index d6d1a2a55cc0..0c7f700b27dd 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -990,9 +990,10 @@ static int arm_smmu_find_sme(struct arm_smmu_device *smmu, u16 id, u16 mask) * expect simply identical entries for this case, but there's * no harm in accommodating the generalisation. */ - if ((mask & smrs[i].mask) == mask && - !((id ^ smrs[i].id) & ~smrs[i].mask)) + + if (smr_is_subset(&smrs[i], id, mask)) return i; + /* * If the new entry has any other overlap with an existing one, * though, then there always exists at least one stream ID diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 703fd5817ec1..2e4f65412c6b 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -501,6 +501,11 @@ static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page, writeq_relaxed(val, arm_smmu_page(smmu, page) + offset); } +static inline bool smr_is_subset(struct arm_smmu_smr *smrs, u16 id, u16 mask) +{ + return (mask & smrs->mask) == mask && !((id ^ smrs->id) & ~smrs->mask); +} + #define ARM_SMMU_GR0 0 #define ARM_SMMU_GR1 1 #define ARM_SMMU_CB(s, n) ((s)->numpage + (n))